Abstract: A nanowire transistor includes a channel structure on a substrate, a gate structure on and around the channel structure, a source/drain structure adjacent to two sides of the gate structure, and a contact plug connected to the source/drain structure. Preferably, the source/drain structure includes graphene and the contact plug further includes a silicide layer on the source/drain structure, a graphene layer on the silicide layer, and a barrier layer on the graphene layer.

Abstract: The invention provides a layout pattern of a semiconductor varactor, which comprises a plurality of varactor units arranged on a substrate, wherein each varactor unit comprises a plurality of fin structures arranged in parallel with each other, a plurality of gate structures arranged in parallel with each other, located on the substrate and spanning the fin structures, and a gate metal layer electrically connected with the plurality of gate structures.

Abstract: The device of reusable balloons includes a rubber balloon and a base. The rubber balloon has a neck. After the balloon is inflated, the neck is twisted to form multiple tight spirals whose flexibility and pressure prevents air leakage, and the neck is tied into a loose single knot. The base has a first through hole and a second through hole arranged radially away from the base's center. A slit is provided connecting the first and second through holes that is selectively and flexibly opened. After the single knot is run through the first through hole, the neck is plugged into the second through hole through the slit. Four or more rubber balloons can be attached to the base and multiple bases can be coupled and arranged to decorate events. After the event, the single knot can be undone, allowing the balloon to deflate and be stored for repeated use.

Abstract: The present disclosure provides a semiconductor device package. The semiconductor device package includes an antenna layer, a first circuit layer and a second circuit layer. The antenna layer has a first coefficient of thermal expansion (CTE). The first circuit layer is disposed over the antenna layer. The first circuit layer has a second CTE. The second circuit layer is disposed over the antenna layer. The second circuit layer has a third CTE. A difference between the first CTE and the second CTE is less than a difference between the first CTE and the third CTE.

Abstract: A secure boot device includes a counter, a storage device and a comparator. The counter receives a clock. When the processor performs a verification of a firmware for the first time, the counter counts a first verification time taken by the processor to perform the verification of the firmware for the first time based on the clock to generate a first-time verification count value. When the processor performs the verification of the firmware for the non-first time, the counter counts a second verification time taken by the processor to perform the verification of the firmware at least once for the non-first time based on the clock to generate a count value. The storage device stores the first-time verification count value. The comparator is electrically connected to the counter and the storage device. When the processor performs the verification of the firmware for the non-first time, the comparator compares the count value with the first-time verification count value, and generates a comparison result.

Abstract: A camera driving module includes: a base including a central opening; a casing disposed on the base and including an opening hole corresponding to the central opening; a lens unit movably disposed on the casing; and a focus driving part. The focus driving part includes a carrier, an AF coil element, at least two permanent magnets and a Hall element. The carrier is disposed on the lens unit and movable in a direction parallel to an optical axis. The AF coil element is fixed to the base and faces toward the carrier. The permanent magnets are fixed on one side of the carrier facing toward the base and disposed opposite to each other about the optical axis. The Hall element faces toward a corresponding surface of one of the permanent magnets. The AF coil element and the corresponding surfaces are arranged in the direction parallel to the optical axis.

Abstract: A tool connector is provided, including: a main body, including a connection portion including a through hole, a blocking member being movably received in the through hole; an adapter member, inserted in the main body and movable between a first position and a second position, wherein when the adapter member is located in the first position, the adapter member is abutted radially against the blocking member so that the blocking member is urged outwardly, and when the adapter member is located in the second position, the blocking member is not urged outwardly by the adapter member so that the blocking member is inwardly movable; an elastic member, disposed between the main body and the adapter member, urging the adapter member toward the first position; at least one detent member, disposed on the main body, configured to block the adapter member from detaching from the main body.

Abstract: An inverted F-shaped single-band antenna structure includes a ground terminal, an impedance-matching terminal, a radiation terminal, and a signal feed-in terminal. The ground terminal includes a body. The impedance-matching terminal is bent and extended from the body, and is connected perpendicularly to the body. The radiation terminal is bent and extended from the impedance-matching terminal, and is connected perpendicularly to the impedance-matching terminal, and is arranged correspondingly with the body. The signal feed-in terminal is bent and extended from the radiation terminal, and connected perpendicularly to the radiation terminal, and arranged correspondingly with the impedance-matching terminal, and not connected to the body.

Abstract: A dual-band antenna structure includes a ground terminal, an impedance-matching terminal, a radiation terminal, and a signal feed-in terminal. The ground terminal includes a body. The impedance-matching terminal is bent and extended from one side of the body, and connected perpendicularly to the body. The radiation terminal is bent and extended from one side of the impedance-matching terminal, and connected perpendicularly to the impedance-matching terminal. The signal feed-in terminal is bent and extended from one side of the radiation terminal, and connected perpendicularly to the radiation terminal, and connected to the impedance-matching terminal on a same side, and not connected to the ground terminal. A length of the impedance-matching terminal is shortened to increase an area of the radiation terminal and shorten a distance between the ground terminal and the radiation terminal, so the inverted F-shaped antenna structure is arranged inside electronic apparatuses with limited height and space.

Abstract: A single-band antenna structure includes a ground terminal, an impedance-matching terminal, a radiation terminal, and a signal feed-in terminal. The ground terminal includes a body. The impedance-matching terminal is bent and extended from the body, and connected perpendicularly to the body. The radiation terminal is square, and bent and extended from the impedance-matching terminal, and connected perpendicularly to the impedance-matching terminal, and arranged correspondingly with the body. The signal feed-in terminal is bent and extended from the radiation terminal, and connected perpendicularly to the radiation terminal, and connected to the impedance-matching terminal on a same side, and not connected to the ground terminal.

Abstract: An n-type field effect transistor includes semiconductor channel members vertically stacked over a substrate, a gate dielectric layer wrapping around each of the semiconductor channel members, and a work function layer disposed over the gate dielectric layer. The work function layer wraps around each of the semiconductor channel members. The n-type field effect transistor also includes a WF isolation layer disposed over the WF layer and a gate metal fill layer disposed over the WF isolation layer. The WF isolation layer fills gaps between adjacent semiconductor channel members.

Abstract: A method of forming a semiconductor device with an embedded die is provided. The method includes forming a plurality of redistribution traces at a first major side of a package substrate. A cavity is formed in the package substrate. The plurality of redistribution traces substantially surrounding an opening of the cavity at the first major side. A semiconductor die is mounted in the cavity. A wire bond is formed between a bond pad of the semiconductor die and a wiring pad of a redistribution trace of the plurality of redistribution traces. An encapsulant encapsulates the semiconductor die and the first major side of the package substrate. A base region of the redistribution trace is exposed.

Abstract: A heatsink includes a main body, a hinge, an arm portion, and a latch. The arm portion is in physical communication with the main body and with the hinge. The arm portion includes a movable portion that transitions between a closed position and an open position. The latch is in physical communication with the movable portion of the arm portion. The latch transitions between a locked position and an unlocked position. The latch securely holds the movable portion in the closed position.

Abstract: A semiconductor structure includes a substrate, a first transistor disposed over the substrate and including a first channel, a first interfacial layer over the first channel, a first gate dielectric layer over the first interfacial layer, and a first gate electrode layer over the first gate dielectric layer, and a second transistor disposed over the substrate and including a second channel, a second interfacial layer over the second channel, a second gate dielectric layer over the second interfacial layer, and a second gate electrode layer over the second gate dielectric layer. The first gate dielectric layer includes a first dipole material composition having a first maximum concentration at a half-thickness line of the first gate dielectric layer. The second gate dielectric layer includes a second dipole material composition having a second maximum concentration at a half-thickness line of the second gate dielectric layer and greater than the first maximum concentration.

Abstract: A conductive structure includes a core portion, a plurality of electronic devices and a filling material. The core portion defines a cavity. The electronic devices are disposed in the cavity of the core portion. The filling material is disposed between the electronic devices and a sidewall of the cavity of the core portion.

Abstract: A semiconductor substrate structure and a method of manufacturing a semiconductor substrate structure are provided. The semiconductor substrate structure includes a substrate, an electronic device, and a filling material. The substrate defines a cavity. The electronic device is disposed in the cavity and spaced apart from the substrate by a gap. The filling material is disposed in the gap and covers a first region of an upper surface of the electronic device.

Abstract: A nanowire transistor includes a channel structure on a substrate, a gate structure on and around the channel structure, a source/drain structure adjacent to two sides of the gate structure, and a contact plug connected to the source/drain structure. Preferably, the source/drain structure includes graphene and the contact plug further includes a silicide layer on the source/drain structure, a graphene layer on the silicide layer, and a barrier layer on the graphene layer.

Abstract: A semiconductor device includes a first semiconductor layer below a second semiconductor layer; first and second gate dielectric layers surrounding the first and the second semiconductor layers, respectively; and a gate electrode surrounding both the first and the second gate dielectric layers. The first gate dielectric layer has a first top section above the first semiconductor layer and a first bottom section below the first semiconductor layer. The second gate dielectric layer has a second top section above the second semiconductor layer and a second bottom section below the second semiconductor layer. The first top section has a first thickness. The second top section has a second thickness. The second thickness is greater than the first thickness.

Abstract: A semiconductor device package includes a first conductive structure, a stress buffering layer and a second conductive structure. The first conductive structure includes a substrate, at least one first electronic component embedded in the substrate, and a first circuit layer disposed on the substrate and electrically connected to the first electronic component. The first circuit layer includes a conductive wiring pattern. The stress buffering layer is disposed on the substrate. The conductive wiring pattern of the first circuit layer extends through the stress buffering layer. The second conductive structure is disposed on the stress buffering layer and the first circuit layer.

Abstract: Provided is a coil carrier board, including a base coil layer, a conductive layer stacked on and bonded to the base coil layer, at least one build-up coil layer stacked on and bonded to the conductive layer, and an opening connecting the base coil layer, the conductive layer and the build-up coil layer. The coil carrier board has thick copper, fine line spacing and appropriate rigidity by means of the build-up circuit process and the structural design of the insulating layer of a photosensitive dielectric material bonded with a thermosetting dielectric material. Accordingly, the high current-carrying efficiency of the coil carrier board is enhanced, and the overall structure of the coil carrier board has better flatness, rigidity and high interlayer alignment accuracy, thereby facilitating miniaturization and automated assembly production.