Abstract: A lens driving apparatus includes a holder, a cover, a carrier, a first magnet, a coil, a spring, two second magnets and a hall sensor. The holder includes an opening hole. The cover is made of metal material and coupled to the holder. The carrier is movably disposed in the cover, and for coupling to a lens. The first magnet is connected to an inner side of the cover. The coil is wound around an outer side of the carrier, and adjacent to the first magnet. The spring is coupled to the carrier. The second magnets are disposed on one end of the carrier which is toward the holder. The hall sensor is for detecting a magnetic field of any one of the second magnets, wherein the magnetic field is varied according to a relative displacement between the hall sensor and the second magnet which is detected.

Abstract: A multi-rank circuit system includes multiple transmitters each switchably coupled to a first end of a shared input/output (IO) channel and a unified receiver coupled to a second end of the shared IO channel. The unified receiver is coupled to apply an analog reference voltage to set a differential output of the unified receiver, and further configured to apply a variable digital code to adjust the differential output according to a particular one of the transmitters that is switched to the shared IO channel.

Abstract: An apparatus and method for providing a decision feedback equalizer are disclosed herein. In some embodiments, a method and apparatus for reduction of inter-symbol interference (ISI) caused by communication channel impairments is disclosed. In some embodiments, a decision feedback equalizer includes a plurality of delay latches connected in series, a slicer circuit configured to receive an input signal from a communication channel and delayed feedback signals from the plurality of delay latches and determine a logical state of the received input signal, wherein the slicer circuit further comprises a dynamic threshold voltage calibration circuit configured to regulate a current flow between output nodes of the slicer circuit and ground based on the received delayed feedback signal and impulse response coefficients of the communication channel.

Abstract: A facial recognition system and a physiological information generative method are disclosed. The facial recognition system includes a visible light sensor, a thermal imaging sensor, and a processor. The generative method is executed by the processor, using a real-time object detection algorithm. The generative method includes receiving one or more current visible and thermal images, and identifying the nasal area in the current thermal images when a face region in the current visible images is not identifiable by the real-time object detection algorithm in the processor; determining in the processor that respiratory information is abnormal according to the cycles of exhalation and inhalation, as detected through brightness changes in the nostril area; and notifying abnormal respiratory information.

Abstract: The invention provides a layout pattern of a semiconductor varactor, which comprises a plurality of varactor units arranged on a substrate, wherein each varactor unit comprises a plurality of fin structures arranged in parallel with each other, a plurality of gate structures arranged in parallel with each other, located on the substrate and spanning the fin structures, and a gate metal layer electrically connected with the plurality of gate structures.

Abstract: A foldable electronic device is provided, including a first display, a second display, an input unit, a first hinge, a second hinge, and a flat support unit. The first hinge pivotally connects the first display to the second display. The second hinge pivotally connects the second display to the input unit. The first and second hinges are located on opposite sides of the second display, and the support unit is pivotally connected to the rear side of the second display.

Abstract: The invention provides a layout pattern of a semiconductor cell, which comprises a substrate with a first L-shaped MESA region and a second L-shaped MESA region, wherein the shapes of the first L-shaped MESA region and the second L-shaped MESA region are mutually inverted by 180 degrees, a first high electron mobility transistor (HEMT) and a second high electron mobility transistor are located on the first L-shaped MESA region, and a third high electron mobility transistor and a fourth high electron mobility transistor are located on the second L-shaped MESA region.

Abstract: A method for fabricating a nanowire transistor includes the steps of first forming a nanowire channel structure on a substrate, in which the nanowire channel structure includes first semiconductor layers and second semiconductor layers alternately disposed over one another. Next, a gate structure is formed on the nanowire channel structure and then a source/drain structure is formed adjacent to the gate structure, in which the source/drain structure is made of graphene.

Abstract: The present disclosure provides a semiconductor device package. The semiconductor device package includes a first conductive component, a second conductive component, a planarization layer and an antenna layer. The second conductive component is disposed adjacent to the first conductive component. The second conductive component and the first conductive component have different thicknesses. The planarization layer is disposed on the first conductive component. The antenna layer is disposed on the first conductive component and the second conductive component.

Abstract: A secure boot device includes a counter, a storage device and a comparator. The counter receives a clock. When the processor performs a verification of a firmware for the first time, the counter counts a first verification time taken by the processor to perform the verification of the firmware for the first time based on the clock to generate a first-time verification count value. When the processor performs the verification of the firmware for the non-first time, the counter counts a second verification time taken by the processor to perform the verification of the firmware at least once for the non-first time based on the clock to generate a count value. The storage device stores the first-time verification count value. The comparator is electrically connected to the counter and the storage device. When the processor performs the verification of the firmware for the non-first time, the comparator compares the count value with the first-time verification count value, and generates a comparison result.

Abstract: A method for forming a packaged integrated circuit device includes providing a semiconductor wafer having a plurality of integrated circuit devices, each integrated circuit device extending into the semiconductor wafer to a first depth, and grinding a backside of the silicon wafer to no more than the first depth. The method further includes forming a backside cut between the integrated circuit devices. The backside cut extends to within the first depth, but the backside cut does not extend completely through the semiconductor wafer. The backside cut exposes a plurality of edges of each of the integrated circuit devices. The method further includes depositing, on the backside of the wafer, a metallization layer on a bottom surface of the integrated circuit devices and on the edges.

Abstract: The present disclosure provides a semiconductor device package. The semiconductor device package includes an antenna layer, a first circuit layer and a second circuit layer. The antenna layer has a first coefficient of thermal expansion (CTE). The first circuit layer is disposed over the antenna layer. The first circuit layer has a second CTE. The second circuit layer is disposed over the antenna layer. The second circuit layer has a third CTE. A difference between the first CTE and the second CTE is less than a difference between the first CTE and the third CTE.

Abstract: A method includes forming a dielectric layer on a semiconductor workpiece, forming a first patterned layer of a first dipole material on the dielectric layer, and performing a first thermal drive-in operation at a first temperature to form a diffusion feature in a first portion of the dielectric layer beneath the first patterned layer. The method also includes forming a second patterned layer of a second dipole material, where a first section of the second patterned layer is on the diffusion feature and a second section of the second patterned layer is offset from the diffusion feature. The method further includes performing a second thermal drive-in operation at a second temperature, where the second temperature is less than the first temperature. The method additionally includes forming a gate electrode layer on the dielectric layer.

Abstract: An integrated antenna package structure includes a first redistribution structure, a first chip, a heat dissipation structure, a second chip, and an antenna structure. The first chip is located on a first side of the first redistribution structure, and is electrically connected to the first redistribution structure. The heat dissipation structure is thermally connected to the first chip, and the first chip is located between the heat dissipation structure and the first redistribution structure. The second chip is located on a second side of the first redistribution structure opposite to the first side, and is electrically connected to the first redistribution structure. The antenna structure is electrically connected to the first redistribution structure.

Abstract: An electronic device package and method of fabricating such a package includes a first and second components encapsulated in a volume of molding material. A surface of the first component is bonded to a surface of the second component. Upper and lower sets of redistribution lowers that include, respectively, first and second sets of conductive interconnects are formed on opposite sides of the molding material. A through-package interconnect passes through the volume of molding material and has ends that terminate, respectively, within the upper set of redistribution layers and within the lower set of redistribution layers.

Abstract: A semiconductor device includes a first semiconductor layer below a second semiconductor layer; first and second gate dielectric layers surrounding the first and the second semiconductor layers, respectively; and a gate electrode surrounding both the first and the second gate dielectric layers. The first gate dielectric layer has a first top section above the first semiconductor layer and a first bottom section below the first semiconductor layer. The second gate dielectric layer has a second top section above the second semiconductor layer and a second bottom section below the second semiconductor layer. The first top section has a first thickness. The second top section has a second thickness. The second thickness is greater than the first thickness.

Abstract: A package is formed that encapsulates first and second components having respective first and second thickness differing from each other. Each component has lower surface provided with electrical contact pads and an upper surface opposite the lower surface. A volume of molding material encapsulates the first component. The package includes a set redistribution layers including a set of electrically-conductive interconnects surrounded by electrically-insulating material. The redistribution layers are disposed above the upper surface of the first component. The package includes one or more electrically conductive interconnects that pass through the redistribution layers to the lower surface of the first component; The second component is disposes at a location adjacent to the first component. A first portion of the second component is surrounded by the volume of molding material and a second portion of the second component is surrounded by one or more of the redistribution layers.

Abstract: A light-emitting element includes a semiconductor light-emitting stack including a first semiconductor layer, a second semiconductor layer formed on the first semiconductor layer, and an active layer formed therebetween; a first conductive layer disposed on the second semiconductor layer and electrically connecting the second semiconductor layer; a second conductive layer disposed on the second semiconductor layer and electrically connecting the first semiconductor layer; and a cushion part disposed on and directly contacts the first conductive layer, wherein in a top view, the cushion part is surrounded by and electrically isolated from the second conductive layer.

Abstract: A chip package structure including a heat dissipation base, a first redistribution layer, a second redistribution layer, at least one chip, at least one metal stack, a plurality of conductive structures, and an encapsulant is provided. The second redistribution layer is disposed on the heat dissipation base and thermally coupled to the heat dissipation base. The chip, the metal stack, and the conductive structures are disposed between the second redistribution layer and the first redistribution layer. An active surface of the chip is electrically connected to the first redistribution layer and an inactive surface of the chip is thermally coupled to the second redistribution layer via the metal stack. The first redistribution layer is electrically connected to the second redistribution layer via the conductive structures. The encapsulant is filled between the second redistribution layer and the first redistribution layer. A manufacturing method of a chip package structure is also provided.

Abstract: A power transceiver device includes a housing, a circuit module and an electrical connector. The circuit module is located within the housing. The electrical connector includes a terminal base and two conductive terminals. The terminal base is fixed on one side surface of the housing. Each of the conductive terminals includes a sheet, an extending portion and an opening. One end of the sheet extends through a front face of the terminal base, another end thereof is electrically connected to the circuit module. The extending portion extends transversely from the end of the sheet, the opening is firmed on the extending portion, and a virtual axis of the opening passes through the front lateral face of the terminal base. The conductive terminals are switchably electrically connected to each other.