Abstract: A fabrication method for a memory device with a floating gate is provided. A substrate is provided. A channel doping step is performed on the substrate, wherein the actual threshold voltage of the subsequently formed memory device becomes greater than the preset threshold voltage. A stack gate and source/drain regions are then sequentially formed on the substrate to complete the formation of the memory device. The drain-turn-on leakage is prevented by an increase of the actual threshold voltage.

Abstract: A macro model of a programmable NROM for simulating the characters of the NROM under programming operation. Charges are stored in a portion of the nitride material layer to for a charge trapped region when the NROM is programmed. A normal MOS symbol element and a short channel MOS symbol element are respectively represent a MOS without having the charge trapped region and a MOS with a charge trapped region. Moreover, the normal MOS symbol element is series with the short channel MOS symbol element, wherein a source of the short channel MOS symbol element is coupled with a drain of the normal MOS symbol element.

Abstract: A process for fabricating CMOS transistor of IC devices that is free from short-changed effects is disclosed. The process of fabrication first forms a gate structure that has a gate polysilicon on top of a gate oxide layer on the surface of the IC substrate. A first spacer is then formed on the sidewall of the gate structure. Lightly-doped source/drain regions are then formed for the transistor by implanting impurities into the source/drain regions of the transistor. A second sidewall spacer then covers the first sidewall spacer. Heavily-doped source/drain regions underneath the lightly-doped source/drain regions are then formed by performing a source/drain implantation procedure. Finally, impurities in the lightly- and heavily-doped source/drain regions are then driven-in into the channel region of the transistor in a rapid thermal annealing procedure.

Abstract: A qualification test method for a non-volatile memory includes determining a relation curve between the programming voltage and the lifetime of the memory cell. A programming voltage with respect to the memory array within the expected lifetime is estimated. According to the relation curve, the accelerating test voltage and the test time period corresponding to the programming voltage operated in the expected lifetime are computed out. The test is performed for the test time period under the accelerating test voltage. All the memory cells at the programmed state are tested to see if the original programmed state still remains. If the programmed state remains, the memory array is judged to have the life period. If the programmed state does not remain, the memory array is judged to have no the life period.

Abstract: A method of controlling the multi-state NROM. A program is executed to inject electric charges that are trapped inside a nitride layer of the NROM. The amount of electric charges trapped inside the nitride layer is controlled so that the memory cell can have different threshold voltages. To read from the memory cell, a first variable voltage is applied to the gate electrode. According to the range of a second variable voltage applied to the drain terminal, three different potential levels, from the smallest to the largest, including a first potential level, a second potential level and a third potential level are set. The second input voltage is adjusted to the first potential level. When a high current is sensed, a first storage state is assumed. If little current is detected, the second input voltage is adjusted to the second potential level. When a high current is sensed, a second storage state is assumed.

Abstract: A multi-level memory cell device and method for self-converged programming which includes a memory cell switchably coupled to a non-programmable reference cell (or dummy cell), the cells arranged in respective arrays. A current source voltage between the source node and ground of the cells is relational to the threshold voltage, so as the threshold voltage is increased, the current source voltage decreases. The threshold voltage of the dummy cell is set by a stable voltage source. The memory cell is programmed and the current source voltage of the memory cell is compared to the current source voltage of the reference cell and therefore the difference in the voltages can be used to sense convergence of the programmed cell with a target threshold level set on the reference cell. A controller is also included between the reference cell and memory cell for adjusting the threshold voltage of the dummy cell according to the gate coupling ratio of the floating gate memory cell.

Abstract: A method for programming a semiconductor memory device, such as an EPROM or a Flash EPROM, which combines the advantages of ramping down a source voltage with the advantages associated with increasing a gate voltage. A programming period is divided into a program disturbance inhibited period and a program period. The programming period is further divided into sub-program periods, with each sub-program period having a program disturbance and a program period. A wordline WL voltage may increase with each sub-program period to improve the programming speed. Also, the program disturbance period may only be performed for the first sub-program period. Each sub-program period may also include a verify period, in order to implement a program and verify technique suitable for programming multi-level Flash EPROMS.