Abstract: A method for manufacturing an electrically programmable non-volatile memory cell comprises forming a first electrode on a substrate, forming an inter-electrode layer of material on the first electrode having a property which is characterized by progressive change in response to stress, and forming a second electrode over the inter-electrode layer of material. The inter-electrode layer comprises a dielectric layer, such as ultra-thin oxide, between the first and second electrodes. A programmable resistance, or other property, is established by stressing the dielectric layer, representing stored data. Embodiments of the memory cell are adapted to store multiple bits of data per cell and/or adapted for programming more than one time without an erase process.

Abstract: One embodiment of the present invention provides a system having a nonvolatile memory comprising a p type semiconductor substrate, an oxide layer over the p type semiconductor substrate, a nitride layer over the oxide layer, an additional oxide layer over the nitride layer, a gate over the additional oxide layer, two N+ junctions in the p type semiconductor layer, a source and drain respectively formed in the two N+ junctions, a first bit and a second bit in the nonvolatile memory, and accordingly at least two states of operation (i.e., erase and program) therefor. That is, one bit in the nonvolatile memory can either be in an erase state or program state. For erasing a bit, electrons are injected at the gate of the nonvolatile memory. For programming a bit, electric holes are injected or electrons are reduced for that bit.

Abstract: The invention provides a nonvolatile memory and corresponding method having an optimal memory erase function and, more particularly, a method for erasing a nonvolatile memory comprising a source, a gate, a drain, a channel and a trapping layer. The method according to a preferred embodiment of the invention generally comprises the steps of applying a non-zero gate voltage to the gate, applying a non-zero source voltage to the source, applying a non-zero drain voltage to the drain in each erase shot wherein the drain voltage is generally higher in magnitude than the source voltage, generating hot holes in the nonvolatile memory, injecting the generated hot holes in the trapping layer near drain junction, and accordingly erasing the nonvolatile memory.

Abstract: A method of programming the memory cell comprises setting the memory cell to an initial state of a first gate threshold voltage, performing a processing sequence including: applying a voltage bias between the gate and the first junction region to cause electric hole to migrate towards and be retained in the trapping layer, and evaluating a read current generated in response to the voltage bias to determine whether a second gate threshold voltage is reached, wherein the second gate threshold voltage is lower than the first gate threshold voltage. The processing sequence is repeated a number of times by varying one or more time the voltage bias between the gate and the first junction region until the second gate threshold voltage is reached and the memory cell is in a program state.

Abstract: A NAND-type erasable programmable read only memory (EEPROM) device formed of a number of substantially identical EEPROM cells with each EEPROM cell being capable of storing two bits of information. A simple method for operating the memory comprises erasing, programming, and reading the device.

Abstract: A method for programming a non-volatile memory is described. In the method, a reference level is selected according to the level distribution of the memory cells in a storage state, and then predetermined memory cells are programmed to a next storage state according to the reference level. The reference level falls between the cell level distribution of the storage state and that of the next storage state.

Abstract: A process and a memory architecture for operating a charge trapping memory cell is provided. The method for operating the memory cell includes establishing a high threshold state in the memory cell by injecting negative charge into the charge trapping structure to set a high state threshold. The method includes using a self-converging biasing procedure to establish a low threshold state for the memory cell by reducing the negative charge in the charge trapping structure to set the threshold voltage for the cell to a low threshold state. The negative charge is reduced in the memory cell by applying a bias procedure including at least one bias pulse. The bias pulse balances charge flow into and out of the charge trapping layer to achieve self-convergence on a desired threshold level. Thereby, an over-erase condition is avoided.

Abstract: A method of operating a non-volatile memory cell, wherein the non-volatile memory cell includes a word line, a first bit line, and a second bit line, the method includes programming the memory cell that includes applying a high positive bias to the first bit line, applying a ground bias to the second bit line, and applying a high negative bias to the word line, wherein positively-charged holes tunnel through the dielectric layer into the trapping layer.

Abstract: An erasing method for the memory cells of a non-volatile memory is provided. Each memory cell comprises a gate, a source, a drain, an electron-trapping layer and a substrate. The data within the memory cell is erased by applying a first voltage to the control gate, applying a second voltage to the source, applying a third voltage to the drain and applying a fourth voltage to the substrate. The electrons are pulled from the electron-trapping layer into the channel by negative gate F-N tunneling effect.

Abstract: A memory core includes a bit line and a word line. The memory core also includes a core cell in electrical communication with the word line and the bit line. The core cell includes a threshold changing material. The threshold changing material is programmed to enable access to the core cell based upon a voltage applied to the word line. Methods for accessing a memory core cell also are described.

Abstract: The invention provides a nonvolatile memory and corresponding method having an optimal memory erase function and, more particularly, a method for erasing a nonvolatile memory comprising a source, a gate, a drain, a channel and a trapping layer. The method according to a preferred embodiment of the invention generally comprises the steps of applying a non-zero gate voltage to the gate, applying a non-zero source voltage to the source, applying a non-zero drain voltage to the drain in each erase shot wherein the drain voltage is generally higher in magnitude than the source voltage, generating hot holes in the nonvolatile memory, injecting the generated hot holes in the trapping layer near drain junction, and accordingly erasing the nonvolatile memory.

Abstract: A macro model of a programmable NROM for simulating the characters of the NROM under programming operation. Charges are stored in a portion of the nitride material layer to for a charge trapped region when the NROM is programmed. A normal MOS symbol element and a short channel MOS symbol element are respectively represent a MOS without having the charge trapped region and a MOS with a charge trapped region. Moreover, the normal MOS symbol element is series with the short channel MOS symbol element, wherein a source of the short channel MOS symbol element is coupled with a drain of the normal MOS symbol element.

Abstract: An erasing method for the memory cells of a non-volatile memory is provided. Each memory cell comprises a gate, a source, a drain, an electron-trapping layer and a substrate. The data within the memory cell is erased by applying a first voltage to the control gate, applying a second voltage to the source, applying a third voltage to the drain and applying a fourth voltage to the substrate. The electrons are pulled from the electron-trapping layer into the channel by negative gate F-N tunneling effect.

Abstract: A non-volatile memory device is described, comprising a plurality of memory cells, a plurality of word lines, a plurality of drain lines, and a plurality of source lines, wherein two adjacent memory cells in a column constitute a cell pair, and all cell pairs are arranged in rows and columns. The two memory cells in each cell pair share a source region, and two adjacent cell pairs in a column share a drain region. The source regions and the gates of the memory cells in the same row are coupled to a source line and a word line, respectively, and the drain regions of the memory cells in the same column are coupled to a drain line.

Abstract: A method of a read scheme for a non-volatile memory cell. The non-volatile memory cell includes a substrate, a source, a drain and a gate above a channel separated by a nonconducting charge trapping material sandwiched between first and second insulating layers. The method applies a first positive drain-to-source bias, a second positive source-to-substrate bias, and a third positive gate-to-source bias to read the source-side charges trapped in the trapping material near the source side.

Abstract: An erasing method for the memory cells of a non-volatile memory is provided. Each memory cell comprises a gate, a source, a drain, an electron-trapping layer and a substrate. The data within the memory cell is erased by applying a first voltage to the control gate, applying a second voltage to the source, applying a third voltage to the drain and applying a fourth voltage to the substrate. The electrons are pulled from the electron-trapping layer into the channel by negative gate F-N tunneling effect.

Abstract: A method of programming the memory cell comprises setting the memory cell to an initial state of a first gate threshold voltage, performing a processing sequence including: applying a voltage bias between the gate and the first junction region to cause electric hole to migrate towards and be retained in the trapping layer, and evaluating a read current generated in response to the voltage bias to determine whether a second gate threshold voltage is reached, wherein the second gate threshold voltage is lower than the first gate threshold voltage. The processing sequence is repeated a number of times by varying one or more time the voltage bias between the gate and the first junction region until the second gate threshold voltage is reached and the memory cell is in a program state.

Abstract: One embodiment of the present invention provides a system having a nonvolatile memory comprising a p type semiconductor substrate, an oxide layer over the p type semiconductor substrate, a nitride layer over the oxide layer, an additional oxide layer over the nitride layer, a gate over the additional oxide layer, two N+ junctions in the p type semiconductor layer, a source and drain respectively formed in the two N+ junctions, a first bit and a second bit in the nonvolatile memory, and accordingly at least two states of operation (i.e., erase and program) therefor. That is, one bit in the nonvolatile memory can either be in an erase state or program state. For erasing a bit, electrons are injected at the gate of the nonvolatile memory. For programming a bit, electric holes are injected or electrons are reduced for that bit.

Abstract: The invention advantageously provides a device and method for optimal data retention in a trapping nonvolatile memory cell. A preferred embodiment of the invention provides a trapping nonvolatile memory cell comprising a semiconductor substrate further comprising a source, a drain spaced from the source, and a channel region formed between the source and the drain, a first isolating layer overlying the channel region, a nonconducting charge trapping layer overlying the first isolating layer and trapping electrical charges therein using charge injection, a second isolating layer overlying the trapping layer, and a gate overlying the second isolating layer. After the charges are trapped in the trapping layer, some of the trapped charges are detrapped using electrical field enhanced electron detrapping technique. The charges in the trapping layer are repeatedly trapped and detrapped shallow traps until a desired number of the deep traps are stored in the trapping layer.

Abstract: A non-volatile memory device is described, comprising a plurality of memory cells, a plurality of word lines, a plurality of drain lines, and a plurality of source lines, wherein two adjacent memory cells in a column constitute a cell pair, and all cell pairs are arranged in rows and columns. The two memory cells in each cell pair share a source region, and two adjacent cell pairs in a column share a drain region. The source regions and the gates of the memory cells in the same row are coupled to a source line and a word line, respectively, and the drain regions of the memory cells in the same column are coupled to a drain line.