Patents by Inventor Wen Jer Tsai

Wen Jer Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • OPERATION METHODS FOR MEMORY CELL AND ARRAY FOR REDUCING PUNCH THROUGH LEAKAGE
    Publication number: 20120002484
    Abstract: A method for programming a first memory cell in a memory array. In a specific embodiment, each memory cell has a drain, a source, a channel, and a control gate overlying a charge storage material and the channel. The source of the first memory cell is coupled to the drain of a second memory cell. A voltage is applied to the drain of the first memory cell, and the source of the second memory cell is grounded. The method includes floating the drain of the second memory cell and the source of the first memory cell and turning on the channels of the first and second memory cells, effectively forming an extended channel region. Hot carriers are injected to the charge storage material of the first cell to program the first memory cell. The extended channel lowers electrical fields and reduces punch through leakage in unselected memory cells.
    Type: Application
    Filed: June 13, 2011
    Publication date: January 5, 2012
    Applicant: Macronix International Co., Ltd.
    Inventors: LIT-HO CHONG, Wen-Jer Tsai, Tien-Fan Ou, Jyun-Siang Huang
  • HOT CARRIER PROGRAMMING IN NAND FLASH
    Publication number: 20110305088
    Abstract: A memory device includes a plurality of memory cells arranged in series in the semiconductor body, such as a NAND string, having a plurality of word lines. A selected memory cell is programmed by hot carrier injection using a boosted channel potential to establish the heating field. Boosted channel hot carrier injection can be based on blocking flow of carriers between a first side of a selected cell and a second side of the selected cell in the NAND string, boosting by capacitive coupling the first semiconductor body region to a boosted voltage level, biasing the second semiconductor body region to a reference voltage level, applying a program potential greater than a hot carrier injection barrier level to the selected cell and enabling flow of carriers from the second semiconductor body region to the selected cell to cause generation of hot carriers.
    Type: Application
    Filed: June 10, 2010
    Publication date: December 15, 2011
    Applicant: Macronix International Co., Ltd.
    Inventors: JYUN-SIANG HUANG, Wen-Jer Tsai
  • OPERATION METHODS FOR MEMORY CELL AND ARRAY FOR REDUCING PUNCH THROUGH LEAKAGE
    Publication number: 20110242891
    Abstract: A method for programming a first memory cell in a memory array. In a specific embodiment, each memory cell has a drain, a source, a channel, and a control gate overlying a charge storage material and the channel. The source of the first memory cell is coupled to the drain of a second memory cell. A voltage is applied to the drain of the first memory cell, and the source of the second memory cell is grounded. The method includes floating the drain of the second memory cell and the source of the first memory cell and turning on the channels of the first and second memory cells, effectively forming an extended channel region. Hot carriers are injected to the charge storage material of the first cell to program the first memory cell. The extended channel lowers electrical fields and reduces punch through leakage in unselected memory cells.
    Type: Application
    Filed: June 13, 2011
    Publication date: October 6, 2011
    Applicant: Macronix International Co., Ltd.
    Inventors: LIT-HO CHONG, WEN-JER TSAI, TIEN-FAN OU, JYUN-SIANG HUANG
  • Electrically isolated gated diode nonvolatile memory
    Patent number: 7995384
    Abstract: A gated diode nonvolatile memory cell with a charge storage structure includes a diode structure with an additional gate terminal. Adjacent memory devices are electrically isolated. Example embodiments include the individual memory cell, an array of such memory cells, methods of operating the memory cell or array of memory cells, and methods of manufacturing the same.
    Type: Grant
    Filed: August 15, 2008
    Date of Patent: August 9, 2011
    Assignee: Macronix International Co., Ltd.
    Inventors: Tien-Fan Ou, Wen-Jer Tsai, Jyun-Siang Huang
  • Operation methods for memory cell and array for reducing punch through leakage
    Patent number: 7974127
    Abstract: A method for programming a first memory cell in a memory array. In a specific embodiment, each memory cell has a drain, a source, a channel, and a control gate overlying a charge storage material and the channel. The source of the first memory cell is coupled to the drain of a second memory cell. A voltage is applied to the drain of the first memory cell, and the source of the second memory cell is grounded. The method includes floating the drain of the second memory cell and the source of the first memory cell and turning on the channels of the first and second memory cells, effectively forming an extended channel region. Hot carriers are injected to the charge storage material of the first cell to program the first memory cell. The extended channel lowers electrical fields and reduces punch through leakage in unselected memory cells.
    Type: Grant
    Filed: November 4, 2008
    Date of Patent: July 5, 2011
    Assignee: Macronix International Co., Ltd.
    Inventors: Lit-Ho Chong, Wen-Jer Tsai, Tien-Fan Ou, Jyun-Siang Huang
  • MEMORY CELL AND MANUFACTURING METHOD THEREOF AND MEMORY STRUCTURE
    Publication number: 20110079840
    Abstract: A memory cell is provided. The memory cell includes a substrate, an isolation layer, a gate, a charge storage structure, a first source/drain region, a second source/drain region and a channel layer. The isolation layer is disposed over the substrate. The gate is disposed over the isolation layer. The charge storage structure is disposed over the isolation layer and the gate. The first source/drain region is disposed over the charge storage structure at two sides of the gate. The second source/drain region is disposed over the charge storage structure at top of the gate. The channel layer is disposed over the charge storage structure at sidewall of the gate and is electrically connected with the first source/drain region and the second source/drain region.
    Type: Application
    Filed: October 1, 2009
    Publication date: April 7, 2011
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Jyun-Siang Huang, Wen-Jer Tsai, Tien-Fan Ou, Cheng-Hsien Cheng
  • Method of programming cell in memory and memory apparatus utilizing the method
    Patent number: 7916551
    Abstract: A method of programming a first cell in a memory, wherein the first cell has a first S/D region and shares a second S/D region with a second cell that has a third S/D region opposite to the second S/D region. The channels of the first and the second cells are turned on, a first voltage is applied to the first S/D region, a second voltage is applied to the second S/D region and a third voltage is applied to the third S/D region. The second voltage is between the first voltage and the third voltage, and the first to third voltages make carriers flow from the third S/D region to the first S/D region and cause hot carriers in the channel of the first cell to be injected into the charge storage layer of the first cell.
    Type: Grant
    Filed: June 13, 2008
    Date of Patent: March 29, 2011
    Assignee: MACRONIX International Co., Ltd.
    Inventors: Wen-Jer Tsai, Ta-Hui Wang, Chih-Wei Lee
  • Dynamic random access memory cell and manufacturing method thereof
    Patent number: 7893475
    Abstract: A dynamic random access memory cell including a bottom oxide layer, a first semiconductor layer, a second semiconductor layer, an insulation layer, a gate and a doping layer is provided. The bottom oxide layer is disposed on a substrate. The first semiconductor layer disposed on the bottom oxide layer has a first doping concentration. The second semiconductor layer disposed on the first semiconductor layer has a second doping concentration lower than the first doping concentration. The insulation layer disposed on the bottom oxide layer at least situates at the two sides of the first semiconductor layer. The height of the insulation layer is greater than that of the first semiconductor layer. The gate is disposed on the second semiconductor layer. The doping layer disposed correspondingly to the two sides of the gate substantially contacts the second semiconductor layer and the insulation layer.
    Type: Grant
    Filed: January 24, 2007
    Date of Patent: February 22, 2011
    Assignee: Macronix International Co., Ltd.
    Inventors: Ta-Wei Lin, Wen-Jer Tsai
  • Gated diode nonvolatile memory process
    Patent number: 7888707
    Abstract: A gated diode nonvolatile memory cell with a charge storage structure includes a diode structure with an additional gate terminal. Example embodiments include the individual memory cell, an array of such memory cells, methods of operating the memory cell or array of memory cells, and methods of manufacturing the same.
    Type: Grant
    Filed: October 24, 2007
    Date of Patent: February 15, 2011
    Assignee: Macronix International Co., Ltd.
    Inventors: Yi Ying Liao, Wen Jer Tsai, Chih Chieh Yeh
  • Memory apparatus and method thereof for operating memory
    Patent number: 7864594
    Abstract: A memory apparatus, a controller, and a method thereof for programming non-volatile memory cells are provided. The memory apparatus includes a plurality of memory cells, wherein each memory cell shares a source/drain region with a neighboring memory cell. The method utilizes a compensation electron flow applied into a source/drain region between two memory cells to provide enough electron flow to program one of the two memory cells, even under the circumstances that the other memory cell has a greater threshold voltage, such that the dispersion of the programming speed of the memory cells is reduced.
    Type: Grant
    Filed: October 14, 2008
    Date of Patent: January 4, 2011
    Assignee: Macronix International Co., Ltd.
    Inventors: Wen-Jer Tsai, Tien-Fan Ou, Jyun-Siang Huang
  • Recessed shallow trench isolation
    Patent number: 7804152
    Abstract: In some embodiments, a memory integrated circuit has different shallow trench isolation structures in the memory circuitry of the memory integrated circuit and the control circuitry of the memory integrated circuit. The isolation dielectric fills the trenches of the shallow trench isolation structures to different degrees. In some embodiments, a memory integrated circuit has memory circuitry with shallow trench isolation structures and intermediate regions. The memory circuitry supports a channel between neighboring nonvolatile memory devices supporting multiple current components with different orientations. In some embodiments, recessed shallow trench isolation structures are formed.
    Type: Grant
    Filed: February 25, 2009
    Date of Patent: September 28, 2010
    Assignee: Macronix International Co., Ltd.
    Inventors: Chih Chieh Yeh, Wen Jer Tsai
  • Vertical non-volatile memory
    Patent number: 7795673
    Abstract: A manufacturing method of a vertical non-volatile memory is provided. A first semiconductor layer, a first barrier, a second semiconductor layer, a second barrier and a third semiconductor layer are formed on a substrate sequentially. The first and the third semiconductor layers have a first conductive state, while the second semiconductor layer has a second conductive state. Several strips of active stacked structures are formed by removing portions of the first, second and third semiconductor layers, and portions of the first and second barrier on the substrate. After forming a storage structure on the substrate, the storage structure is covered with a conductive layer filling spaces among the active stacked structures. A portion of the conductive layer is removed to form word lines across the active stacked structures.
    Type: Grant
    Filed: July 23, 2007
    Date of Patent: September 14, 2010
    Assignee: Macronix International Co., Ltd.
    Inventors: Tien-Fan Ou, Wen-Jer Tsai
  • METHOD OF MANUFACTURING MEMORY DEVICES
    Publication number: 20100227441
    Abstract: Disclosed is a memory device and method of operation thereof. The memory device may include a source region and a drain region of a first dopant type, the source and drain regions contain a first semiconductor material; a body region of a second dopant type, the body region being sandwiched between the source and drain regions, the body comprising a second semiconductor material; a gate dielectric layer over at least the body region; and a gate comprising a conductive material over the gate dielectric layer. Specifically, one of the first semiconductor material and the second semiconductor material is lattice matched with the other of the first semiconductor material and the second semiconductor material and has an energy gap smaller than the energy gap of the other of the first semiconductor material and the second semiconductor material.
    Type: Application
    Filed: May 24, 2010
    Publication date: September 9, 2010
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Ta-Wei Lin, Wen-Jer Tsai
  • Gated diode nonvolatile memory structure with diffusion barrier structure
    Patent number: 7768825
    Abstract: A gated diode nonvolatile memory cell with a charge storage structure includes a diode structure with an additional gate terminal and a diffusion barrier structure between the diode nodes. Example embodiments include the individual memory cell, an array of such memory cells, methods of operating the memory cell or array of memory cells, and methods of manufacturing the same.
    Type: Grant
    Filed: January 2, 2007
    Date of Patent: August 3, 2010
    Assignee: Macronix International Co., Ltd.
    Inventors: Hsuan Ling Kao, Wen Jer Tsai, Tien Fan Ou
  • MEMORY ARRAY AND METHOD FOR MANUFACTURING AND OPERATING THE SAME
    Publication number: 20100176437
    Abstract: The invention provides a memory array. The memory array comprises a substrate, a plurality of word lines, a charge trapping structure, a plurality of trench channels and a plurality of bit lines. The word lines are located over the substrate and the word lines are parallel to each other. The charge trapping structure covers a surface of each of the word lines. The trench channels are located over the substrate and the word lines and the trench channels are alternatively arranged and each trench channel is separated from the adjacent word lines by the charge trapping structure. The bit lines are located over the word lines and each bit line is across over each of the word lines and each trench channel is electrically coupled to the bit lines.
    Type: Application
    Filed: January 13, 2009
    Publication date: July 15, 2010
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Jyun-Siang Huang, Wen-Jer Tsai, Tien-Fan Ou
  • Dynamic random access memory cell and manufacturing method thereof
    Patent number: 7754544
    Abstract: A dynamic random access memory cell and a manufacturing method thereof are provided. First, a substrate on which a bottom oxide layer and a semiconductor layer are formed is provided. The semiconductor layer is formed on the bottom oxide layer. Next, a gate is formed on the semiconductor layer. Then, the semiconductor layer is patterned to expose a portion of the bottom oxide layer. Afterwards, an insulation layer is formed at the side walls of the semiconductor layer, wherein the height of the insulation layer is shorter than that of the semiconductor layer, so that a gap is formed between the tops of the insulation layer and the semiconductor layer. Further, a doping layer covering the insulation layer and having the same height with the semiconductor layer is formed on the bottom oxide layer. The doping layer contacts the side walls of the semiconductor layer via the gap.
    Type: Grant
    Filed: September 30, 2009
    Date of Patent: July 13, 2010
    Assignee: Macronix International Co., Ltd.
    Inventors: Ta-Wei Lin, Wen-Jer Tsai
  • Memory device
    Patent number: 7750368
    Abstract: Disclosed is a memory device and method of operation thereof. The memory device may include a source region and a drain region of a first dopant type, the source and drain regions contain a first semiconductor material; a body region of a second dopant type, the body region being sandwiched between the source and drain regions, the body comprising a second semiconductor material; a gate dielectric layer over at least the body region; and a gate comprising a conductive material over the gate dielectric layer. Specifically, one of the first semiconductor material and the second semiconductor material is lattice matched with the other of the first semiconductor material and the second semiconductor material and has an energy gap smaller than the energy gap of the other of the first semiconductor material and the second semiconductor material.
    Type: Grant
    Filed: June 13, 2008
    Date of Patent: July 6, 2010
    Assignee: MACRONIX International Co., Ltd.
    Inventors: Ta-Wei Lin, Wen-Jer Tsai
  • Vertical nonvolatile memory cell, array, and operation
    Patent number: 7723757
    Abstract: A vertical nonvolatile memory cell with a charge storage structure includes a charge control structure with three nodes. Example embodiments include the individual memory cell, an array of such memory cells, methods of operating the memory cell or array of memory cells, and methods of manufacturing the same.
    Type: Grant
    Filed: July 6, 2007
    Date of Patent: May 25, 2010
    Assignee: Macronix International Co., Ltd.
    Inventors: Tien Fan Ou, Wen-Jer Tsai, Hsuan Ling Kao, Yi Ying Liao
  • Gated diode nonvolatile memory cell array
    Patent number: 7672157
    Abstract: A memory integrated circuit has memory arrays that are vertically layered. These memory arrays include word lines and bit lines. Intersections between the word lines and the bit lines include a diode and a memory state storage element. The diode and the memory storage element are connected in between a word line and a bit line. The diode at the intersections includes a first diode node and a second diode node. Various aspects of the memory integrated circuit are electrically interconnected in various ways, such as corresponding word lines, corresponding first diode nodes, or corresponding second diode nodes of different memory arrays being electrically interconnected. Various aspects of the memory integrated circuit are isolated in various ways, such as word lines, first diode nodes, or second diode nodes of different memory arrays being isolated.
    Type: Grant
    Filed: December 2, 2008
    Date of Patent: March 2, 2010
    Assignee: Macronix International Co., Ltd.
    Inventors: Yi Ying Liao, Wen Jer Tsai, Chih Chieh Yeh
  • Electrically Isolated Gated Diode Nonvolatile Memory
    Publication number: 20100039867
    Abstract: A gated diode nonvolatile memory cell with a charge storage structure includes a diode structure with an additional gate terminal. Adjacent memory devices are electrically isolated. Example embodiments include the individual memory cell, an array of such memory cells, methods of operating the memory cell or array of memory cells, and methods of manufacturing the same.
    Type: Application
    Filed: August 15, 2008
    Publication date: February 18, 2010
    Applicant: Macronix International Co., Ltd.
    Inventors: Tien-Fan Ou, Wen-Jer Tsai, Jyun-Siang Huang