Abstract: Systems, methods, and devices are described herein for integrated circuit (IC) layout validation. A plurality of IC patterns are collected which include a first set of patterns capable of being manufactured and a second set of patterns incapable of being manufactured. A machine learning model is trained using the plurality of IC patterns. The machine learning model generates a prediction model for validating IC layouts. The prediction model receives data including a set of test patterns comprising scanning electron microscope (SEM) images of IC patterns. Design violations associated with an IC layout are determined based on the SEM images and the plurality of IC patterns. A summary of the design violations is provided for further characterization of the IC layout.

Abstract: A method of manufacturing an integrated circuit includes generating a layout design of the integrated circuit, manufacturing the integrated circuit based on the layout design, and removing a portion of a gate structure of a set of gate structures thereby forming a first and a second gate structure. Generating the layout design includes placing a set of gate layout patterns and a cut feature layout pattern on the first layout level. The cut feature layout pattern extends in a first direction, overlaps the set of gate layout patterns and identifies a location of the portion of the gate structure of the set of gate structures. The set of gate layout patterns correspond to fabricating a set of gate structures. The set of gate layout patterns extending in a second direction and overlapping a set of gridlines that extend in the second direction.

Abstract: Boundary cells may be provided. A boundary of a first functional cell of a circuit is determined. A first plurality of a first type of dummy cells are placed along a first portion of the determined boundary. The first portion extends in a first direction. Each of the first type of dummy cells comprises first pre-defined dimensions. A second plurality of a second type of dummy cells are placed along a second portion of the determined boundary. The second portion extends in a second direction. Each of the second type of dummy cells comprises second pre-defined dimensions. The second pre-defined dimensions is different than the first pre-defined dimensions.

Abstract: Systems, methods, and devices are described herein for integrated circuit (IC) layout validation. A plurality of IC patterns are collected which include a first set of patterns capable of being manufactured and a second set of patterns incapable of being manufactured. A machine learning model is trained using the plurality of IC patterns. The machine learning model generates a prediction model for validating IC layouts. The prediction model receives data including a set of test patterns comprising scanning electron microscope (SEM) images of IC patterns. Design violations associated with an IC layout are determined based on the SEM images and the plurality of IC patterns. A summary of the design violations is provided for further characterization of the IC layout.

Abstract: Systems, methods, and devices are described herein for integrated circuit (IC) layout validation. A plurality of IC patterns are collected which include a first set of patterns capable of being manufactured and a second set of patterns incapable of being manufactured. A machine learning model is trained using the plurality of IC patterns. The machine learning model generates a prediction model for validating IC layouts. The prediction model receives data including a set of test patterns comprising scanning electron microscope (SEM) images of IC patterns. Design violations associated with an IC layout are determined based on the SEM images and the plurality of IC patterns. A summary of the design violations is provided for further characterization of the IC layout.

Abstract: A method for mitigating extreme ultraviolet (EUV) mask defects is disclosed. The method includes the steps of providing a wafer blank, identifying a first plurality of defects on the wafer blank, providing an EUV mask design on top of the wafer blank, identifying non-critical blocks with corresponding stretchable zones on the EUV mask design, overlapping the EUV blank with the EUV mask design, identifying a second plurality of defects, the second plurality of defects are solved, identifying a third plurality of defects, the third plurality of defects are not solved, adjusting the relative locations of the EUV mask design and the EUV blank to solve at least one of the third plurality of defects, and adjusting the locations of at least one of the non-critical blocks within corresponding stretchable zones to solve at least one of the third plurality of defects.

Abstract: A method including decomposing a conflict graph based on a number of masked to be used to manufacture a semiconductor device. The method further includes determining whether the decomposed conflict graph is a simplified graph based on a comparison between the decomposed conflict graph and a stored conflict graph. The method further includes determining whether the decomposed conflict graph is colorable based on a number of masks used to pattern the layer of the semiconductor device. The method further includes indicating that the conflict graph is colorable in response to a determination that the decomposed conflict graph is colorable.

Abstract: Boundary cells may be provided. A boundary of a first functional cell of a circuit is determined. A first plurality of a first type of dummy cells are placed along a first portion of the determined boundary. The first portion extends in a first direction. Each of the first type of dummy cells comprises first pre-defined dimensions. A second plurality of a second type of dummy cells are placed along a second portion of the determined boundary. The second portion extends in a second direction. Each of the second type of dummy cells comprises second pre-defined dimensions. The second pre-defined dimensions is different than the first pre-defined dimensions.

Abstract: A semiconductor device includes a first cell. The first cell includes a first functional feature, a first sensitivity region, at least one anchor node, wherein each of the at least one anchor node is different from the first functional feature, and a number of anchor nodes of the at least one anchor node linked to the first functional feature is based on a position of the first functional feature relative to the first sensitivity region. The semiconductor device further includes a second cell abutting the first cell. The second cell includes a second functional feature, wherein the second functional feature satisfies a minimum spacing requirement with respect to the first functional feature.

Abstract: A standard cell for a semiconductor device includes a plurality of features for performing the functionality of the standard cell. The standard cell further includes a first sensitivity region adjacent to a first edge of the standard cell. The standard cell further includes anchor nodes linked to corresponding features of the plurality of features, wherein a number of anchor nodes linked to each feature of the corresponding features is based on a position of an end of each feature of the corresponding features relative to the first sensitivity region.

Abstract: A method including decomposing a conflict graph based on a number of masked to be used to manufacture a semiconductor device. The method further includes determining whether the decomposed conflict graph is a simplified graph based on a comparison between the decomposed conflict graph and a stored conflict graph. The method further includes determining whether the decomposed conflict graph is colorable based on a number of masks used to pattern the layer of the semiconductor device. The method further includes indicating that the conflict graph is colorable in response to a determination that the decomposed conflict graph is colorable.

Abstract: A method of manufacturing an integrated circuit includes generating a layout design of the integrated circuit, manufacturing the integrated circuit based on the layout design, and removing a portion of a gate structure of a set of gate structures thereby forming a first and a second gate structure. Generating the layout design includes placing a set of gate layout patterns and a cut feature layout pattern on the first layout level. The cut feature layout pattern extends in a first direction, overlaps the set of gate layout patterns and identifies a location of the portion of the gate structure of the set of gate structures. The set of gate layout patterns correspond to fabricating a set of gate structures. The set of gate layout patterns extending in a second direction and overlapping a set of gridlines that extend in the second direction.

Abstract: An integrated circuit includes a first and second set of gate structures. A center of each of the first set of gate structures is separated from a center of an adjacent gate of the first set of gate structures in a first direction by a first pitch. A center of each of the second set of gate structures is separated from a center of an adjacent gate of the second set of gate structures in the first direction by the first pitch. The first and second set of gate structures extend in a second direction. A gate of the first set of gate structures is aligned in the second direction with a corresponding gate of the second set of gate structures. The gate of the first set of gate structures is separated from the corresponding gate of second set of gate structures in the second direction by a first distance.

Abstract: A method of determining colorability of a layer of a semiconductor device includes iteratively decomposing a conflict graph to remove all nodes having fewer links than a threshold number of links. The method further includes determining whether the decomposed conflict graph is a simplified graph based on a comparison between the decomposed conflict graph and a stored conflict graph. The method further includes determining whether the decomposed conflict graph is colorable based on a number of masks used to pattern the layer of the semiconductor device. The method further includes flagging violations in response to a determination that the decomposed conflict graph is not colorable.

Abstract: An integrated circuit includes a first and second set of gate structures. A center of each of the first set of gate structures is separated from a center of an adjacent gate of the first set of gate structures in a first direction by a first pitch. A center of each of the second set of gate structures is separated from a center of an adjacent gate of the second set of gate structures in the first direction by the first pitch. The first and second set of gate structures extend in a second direction. A gate of the first set of gate structures is aligned in the second direction with a corresponding gate of the second set of gate structures. The gate of the first set of gate structures is separated from the corresponding gate of second set of gate structures in the second direction by a first distance.

Abstract: A camera module includes a lens assembly, a voice coil motor assembly, an image sensor assembly and a flash assembly. The lens assembly is installed in the voice coil motor assembly along an optical axis direction, the image sensor assembly is located below the lens assembly, the flash assembly is mounted above the voice coil motor assembly and includes at least one light source located around a lens of the lens assembly, and the light source adapted for providing a flash for the lens. The flash assembly can provide uniform and even flashing light for the lens to improve imaging quality, and provide compact structure to meet the development of the electronic products miniaturization.

Abstract: A camera module includes a lens assembly, a voice coil motor assembly for receiving and driving the lens assembly, and an image sensor assembly located below the voice coil motor assembly. The voice coil motor assembly comprises a bottom unit that is hollow and a color filter supported by the bottom unit, the color filter, the lens assembly and the image sensor assembly are coaxial, the bottom unit has an upper portion and a lower portion that are integrated together, the upper portion is configured around the lens assembly, and the bottom unit is configured below the lens assembly and supports the color filter. The camera module has simple structure and convenient assembly, can reduce total assembly tolerances of the camera module, achieve an accurate optical axis alignment between the lens and the image sensor, and reduce manufacturing cost to benefit the popularization in industries.

Abstract: A method of determining colorability of a layer of a semiconductor device includes iteratively decomposing a conflict graph to remove all nodes having fewer links than a threshold number of links. The method further includes determining whether the decomposed conflict graph is a simplified graph based on a comparison between the decomposed conflict graph and a stored conflict graph. The method further includes determining whether the decomposed conflict graph is colorable based on a number of masks used to pattern the layer of the semiconductor device. The method further includes flagging violations in response to a determination that the decomposed conflict graph is not colorable.

Abstract: A standard cell for a semiconductor device includes a plurality of features for performing the functionality of the standard cell. The standard cell further includes a first sensitivity region adjacent to a first edge of the standard cell. The standard cell further includes anchor nodes linked to corresponding features of the plurality of features, wherein a number of anchor nodes linked to each feature of the corresponding features is based on a position of an end of each feature of the corresponding features relative to the first sensitivity region.

Abstract: A voice coil motor includes a housing having a cavity; a movable assembly received in the cavity; a fixing assembly configured outside of the movable assembly; and a first spring plate and a second spring plate configured at an upper surface and a lower surface of the movable assembly respectively. The fixing assembly comprises at least two magnetic elements connected with the first spring plate and a spacer member configured on the second spring plate to connect the second spring plate to the magnetic elements or the housing. The voice coil motor is served as an actuator of electronic products such as digital cameras, mobile phones, and digital cameras, which has thin thickness, good performance and strong applicability.