Abstract: A method of making a semiconductor device includes: providing a substrate; forming an insulating layer on the substrate; forming a first trench in the insulating layer; forming a first semiconductor layer in the first trench; and removing a portion of the insulating layer to expose the first semiconductor layer.

Abstract: A method of making a semiconductor device includes: providing a substrate; forming an insulating layer on the substrate; forming a first trench in the insulating layer; forming a first semiconductor layer in the first trench; and removing a portion of the insulating layer to expose the first semiconductor layer.

Abstract: A heterogeneously integrated semiconductor device includes a substrate comprising a first material; a recess formed within the substrate and having a bottom portion with a first width, a top portion with a second width and a middle portion with a third width larger than the first width and the second width; and a first semiconductor layer filled in the bottom portion and including a second material different from the first material.

Abstract: A field-effect transistor structure having two-dimensional transition metal dichalcogenides includes a substrate, a source/drain structure, a two-dimensional (2D) channel layer, and a gate layer. The source/drain structure is disposed on the substrate and has a surface higher than a surface of the substrate. The 2D channel layer is disposed on the source and the drain and covers the space between the source and the drain. The gate layer is disposed between the source and the drain and covers the 2D channel layer. The field-effect transistor having two-dimensional transition metal dichalcogenides is a planar field-effect transistor or a fin field-effect transistor.

Abstract: The present invention relates to an inductive spin-orbit torque device and the method for fabricating the same. The method comprises steps of depositing a two-dimensional thin film using chemical vapor deposition (CVD) and sputtering a ferromagnetic material on the thin film. The crystal structure of the two-dimensional thin film includes at least one lattice plane arranged asymmetrically. The thickness of the two-dimensional thin film includes at least one unit-cell layer. The sum of the at least one unit-cell layer is an odd number. By using the vertical magnetic torque generated by the two-dimensional thin film and the miniaturization in thickness, the device size and the fabrication costs may be reduced.

Abstract: A heterogeneously integrated semiconductor device includes a substrate comprising a first material; a recess formed within the substrate and having a bottom portion with a first width, a top portion with a second width and a middle portion with a third width larger than the first width and the second width; and a first semiconductor layer filled in the bottom portion and including a second material different from the first material.

Abstract: An environment monitoring system is utilized for monitoring an environmental variation status of a riverbed, a lake floor, or a seabed. The environment monitor system includes a wire drawing device configured at a monitoring point for releasing and tightening a transmission wire; a fixing pipe laid between the monitoring point and a structure layer for containing the transmission wire; a plurality of vibration sensing devices respectively configured on the transmission wire for converting sensed vibration energy to a plurality of electric signals and transmitting the plurality of electric signals by the transmission wire; an analyzing device coupled with the wire drawing device and the transmission wire for obtaining a released length of the transmission wire by the wire drawing device and determining the environmental variation status according to the released length and the plurality of electric signals to perform monitoring.

Abstract: A field-effect transistor structure having two-dimensional transition metal dichalcogenides includes a substrate, a source/drain structure, a two-dimensional (2D) channel layer, and a gate layer. The source/drain structure is disposed on the substrate and has a surface higher than a surface of the substrate. The 2D channel layer is disposed on the source and the drain and covers the space between the source and the drain. The gate layer is disposed between the source and the drain and covers the 2D channel layer. The field-effect transistor having two-dimensional transition metal dichalcogenides is a planar field-effect transistor or a fin field-effect transistor.

Abstract: A heterogeneously integrated semiconductor devices includes a base substrate; a Ge-containing film formed on the base substrate; a PMOSFET transistor having a first fin formed on the Ge-containing film; and a NMOSFET transistor having a second fin formed on the Ge-containing film; wherein the PMOSFET transistor and the NMOSFET transistor compose a CMOS transistor, and the first fin comprises Ge-containing material and the second fin comprises a Group III-V compound.

Abstract: A heterogeneously integrated semiconductor devices includes a base substrate; a Ge-containing film formed on the base substrate; a PMOSFET transistor having a first fin formed on the Ge-containing film; and a NMOSFET transistor having a second fin formed on the Ge-containing film; wherein the PMOSFET transistor and the NMOSFET transistor compose a CMOS transistor, and the first fin comprises Ge-containing material and the second fin comprises a Group III-V compound.

Abstract: An environment monitoring system is utilized for monitoring an environmental variation status of a riverbed, a lake floor, or a seabed. The environment monitor system includes a wire drawing device configured at a monitoring point for releasing and tightening a transmission wire; a fixing pipe laid between the monitoring point and a structure layer for containing the transmission wire; a plurality of vibration sensing devices respectively configured on the transmission wire for converting sensed vibration energy to a plurality of electric signals and transmitting the plurality of electric signals by the transmission wire; an analyzing device coupled with the wire drawing device and the transmission wire for obtaining a released length of the transmission wire by the wire drawing device and determining the environmental variation status according to the released length and the plurality of electric signals to perform monitoring.

Abstract: An electrostatic discharge protection apparatus with silicon control rectifier and the method of fabricating the apparatus. Using silicon on insulator technique, a bottom layer, a P-well, a first source/drain region, a second source/drain region and a gate are formed. A selective epitaxial growth region is selectively formed on the first source/drain region, and an N+ region is formed on the bottom layer. The lower portion of the N+ region is then adjacent to the P-well, and the upper portion of the N+ region is adjacent to the gate. Thus, a PNPN silicon control rectifier is formed, and the silicon on insulation CMOS technique is effectively transplanted into the electrostatic discharge apparatus.

Abstract: The front-stage process of a fully depleted SOI device and the structure thereof are described. An SOI substrate having an insulation layer and a crystalline silicon layer above the insulation layer is provided. An isolation layer is formed in the crystalline silicon layer and is connected to the insulation layer to define a first-type MOS active region. An epitaxial suppressing layer is formed above the crystalline silicon layer outside of the first-type MOS active region. A second-type doped epitaxial silicon layer is selectively formed above the crystalline silicon layer in the first-type MOS active region. The second-type doped epitaxial layer is doped in-situ. An undoped epitaxial silicon layer is selectively formed above the second-type doped epitaxial silicon layer. The epitaxial suppressing layer is then removed.

Abstract: The front-stage process of a fully depleted SOI device and the structure thereof are described. An SOI substrate having an insulation layer and a crystalline silicon layer above the insulation layer is provided. An isolation layer is formed in the crystalline silicon layer and is connected to the insulation layer to define a first-type MOS active region. An epitaxial suppressing layer is formed above the crystalline silicon layer outside of the first-type MOS active region. A second-type doped epitaxial silicon layer is selectively formed above the crystalline silicon layer in the first-type MOS active region. The second-type doped epitaxial layer is doped in-situ. An undoped epitaxial silicon layer is selectively formed above the second-type doped epitaxial silicon layer. The epitaxial suppressing layer is then removed.

Abstract: A copper fuse structure for integrated circuit employs two copper pads formed over a semiconductor substrate. The two copper pads are electrically insulated by dielectrics. An aluminum line is utilized to cover and electrically connect the two copper pads.

Abstract: A method for fabricating a metal-oxide semiconductor (MOS) transistor. A substrate having a gate structure is provided. The method of the invention includes forming a liner spacer on each side of the gate structure and a low dopant density region deep inside the substrate. The low dopant density region has a lower dopant density than that of a lightly doped region of the MOS transistor. Then a interchangeable source/drain region with a lightly doped drain (LDD) structure and an anti-punch-through region is formed on each side of the gate structure in the low dopant density region. The depth of the interchangeable source/drain region is not necessary to be shallow.

Abstract: The front-stage process of a fully depleted SOI device and the structure thereof are described An SOI substrate having an insulation layer and a crystalline silicon layer above the insulation layer is provided. An isolation layer is formed in the crystalline silicon layer and is connected to the insulation layer to define a first-type MOS active region. An epitaxial suppressing layer is formed above the crystalline silicon layer outside of the first-type MOS active region A second-type doped epitaxial silicon layer is selectively formed above the crystalline silicon layer in the first-type MOS active region. The second-type doped epitaxial layer is doped in-situ. An undoped epitaxial silicon layer is selectively formed above the second-type doped epitaxial silicon layer. The epitaxial suppressing layer is then removed.

Abstract: The front-stage process of a fully depleted SOI device and the structure thereof are described. An SOI substrate having an insulation layer and a crystalline silicon layer above the insulation layer is provided. An isolation layer is formed in the crystalline silicon layer and is connected to the insulation layer to define a first-type MOS active region. An epitaxial suppressing layer is formed above the crystalline silicon layer outside of the first-type MOS active region. A second-type doped epitaxial silicon layer is selectively formed above the crystalline silicon layer in the first-type MOS active region. The second-type doped epitaxial layer is doped in-situ. An undoped epitaxial silicon layer is selectively formed above the second-type doped epitaxial silicon layer. The epitaxial suppressing layer is then removed.

Abstract: An electrostatic discharge protection apparatus with silicon control rectifier and the method of fabricating the apparatus. Using silicon on insulator technique, a bottom layer, a P-well, a first source/drain region, a second source/drain region and a gate are formed. A selective epitaxial growth region is selectively formed on the first source/drain region, and an N+ region is formed on the bottom layer. The lower portion of the N+ region is then adjacent to the P-well, and the upper portion of the N+ region is adjacent to the gate. Thus, a PNPN silicon control rectifier is formed, and the silicon on insulation CMOS technique is effectively transplanted into the electrostatic discharge apparatus.

Abstract: A salicidation process for a SOI device, comprising a polysilicon gate formed thereon is described. Source/drain regions are formed in the SOI substrate besides the sides of the gate structure. A selective epitaxal growth silicon layer is formed on the source/drain regions and on the gate structure, followed by forming a metal salicide layer on source/drain regions and the gate structure.