Abstract: A method of manufacturing MOS device including the steps of providing a semiconductor substrate that has a device isolation structure thereon, and then depositing a gate oxide layer, a polysilicon layer and an anti-reflection coating in sequence over the substrate. Next, a gate structure is patterned out of the gate oxide layer, the polysilicon layer and the anti-reflection coating. Then, spacers are formed on the sidewalls of the gate structure. Thereafter, a metal silicide layer is formed over source/drain regions. After that, an inter-layer dielectric (ILD) layer is formed over the gate structure and the entire substrate. Then, the inter-layer dielectric layer is planarized to expose the anti-reflection coating. Next, the anti-reflection coating is removed, and then a barrier layer is deposited over the inter-layer dielectric layer and the polysilicon layer. Subsequently, a conductive layer is deposited over the barrier layer.

Abstract: A method for forming a dual damascene structure using low-dielectric constant materials is disclosed. The method includes providing a substrate first. A first dielectric layer is formed on the substrate, and the first dielectric layer is then cured to form a stop layer. Then, a second dielectric layer is formed on the stop layer, and the second dielectric layer is cured to form an insulating layer. The insulating layer, the second dielectric layer, the stop layer, and the first dielectric layer are etched to form a via hole, and the insulating layer and the second dielectric layer is then etched to form a trench line.

Abstract: A static random access memory (SRAM) is disclosed. The SRAM includes a shared contact. A gate oxide layer is firstly formed on a semiconductor substrate, and a polysilicon layer is then formed on the gate oxide layer. A dielectric spacer abuts surface of the polysilicon layer of the SRAM except on a top surface of the expect on a top surface of the polysilicon layer of the SRAM. Moreover, first ions of a first conductive type are implanted between the substrate. And second ions of the first conductive type are implanted into substrate to form a source/drain region of a first gate, and a second gate without the source/drain region using the dielectric spacers as a mask. The SRAM has at least three silicidation regions abutting top surface of the source/drain region, and the first and second gate, and the side wall second gate with no space is also covered a silicidation region. Finally, an inter-layer dielectric (ILD) is deposited over the substrate.

Abstract: A method for fabricating a local interconnect. A gate having a gate oxide layer, a gate polysilicon layer and a cap layer is formed on a provided substrate. A spacer is formed on the sidewall of the gate, and a source/drain region is formed in the substrate. A planarized dielectric layer is formed over the substrate to expose the cap layer. A portion of the dielectric layer and the spacer on one side of the gate is removed to form an opening, so that the source/drain region is exposed. The opening is transformed into a local-interconnect opening by removing the cap layer. A local interconnect is formed by forming a conductive layer in the local-interconnect opening.

Abstract: A method of manufacturing a complementary metal-oxide-semiconductor that utilizes a slight change in the patterned photoresist layer for forming the lightly doped drain structure of an NMOS and the halo implantation region during CMOS fabrication. By forming a photoresist layer that exposes the p-well region where a well pickup structure is to be formed, the distance between the photoresist layer and the gate is increased, thereby eliminating the restrictions imposed upon the tilt angle in a halo implantation. Later, the lightly doped n-type impurities in the well pickup region can be compensated for by the p-type impurity implantation when the PMOS source/drain regions are formed. Hence, the lightly doped n-type well pickup region can be reverted to a p-type impurity doped region.

Abstract: A semiconductor device comprises a semiconductor substrate, a source/drain region formed in the substrate, a gate oxide layer on the substrate between the source/drain region, a conductive layer on the gate oxide layer, a spacer around a side wall of the gate, and an air gap between the gate and the spacer. The spacer is not directly connected with the gate. The air gap is formed between the gate and the spacer.

Abstract: A method of fabricating a capacitor, comprising the steps of: providing a conductive layer over a semiconductor substrate having a transistor formed thereon to connect a source/drain region of the transistor; forming a hemispherical grained silicon layer over the conductive layer; using an implantation method to implant ions into the hemispherical grained silicon layer; performing a thermal treatment process to convert the ions into a barrier layer over the hemispherical grained silicon layer; performing a wet etching process to clean a surface of the barrier layer; forming a dielectric layer over the barrier layer and forming a top electrode over the dielectric layer.

Abstract: A method of forming a shallow trench isolation structure includes etching a substrate to form a trench. Then, an oxide layer is deposited in the trench and over the substrate by using high-density plasma. The oxide layer is pointed since it is formed by high-density plasma chemical vapor deposition. A stop layer made of silicon nitride, silicon oxy-nitride or boron nitride is formed on the oxide layer. The hardness of the stop layer is higher than that of the oxide layer so the protuberance of the oxide layer will be first removed during chemical mechanical polishing.

Abstract: The invention discloses a method of forming a metal-oxide-semiconductor transistor. The method provides a substrate, where a gate structure is formed thereon. Next, a first spacer is formed on the sidewall of the gate structure. A pair of heavily doped regions is formed in the substrate. Then, an annealing process is performed to make the doped ions in the heavily doped regions uniformly distributed. Next, the first spacer is removed and a thin pad dielectric layer is formed over the substrate. Next, a first type halo structure is formed in the bottom portion of the source/drain region beneath the gate structure. A lightly doped region is formed between the gate structure and the first type halo structure and above the first type halo structure. An etching process is performed on the pad dielectric layer to form a second spacer and then the MOS transitor is completed.

Abstract: A method of fabricating a semiconductor device. On a semiconductor substrate comprising a device isolation structure and an active region isolated by the device isolation region, an oxide layer is formed and etched on the active region to form an opening, so that the active within the opening is exposed. A first spacer is formed on a side wall of the opening. A gate oxide layer is formed on the active region within the opening. A conductive layer is formed on the gate oxide layer, so that the opening is filled thereby. The oxide layer is removed. The exposed active region is lightly doped to form a lightly doped region by using the conductive layer and the first spacer as a mask. A second spacer is formed on a side wall of the first spacer and leaves a portion of the first spacer to be exposed. The exposed active region is heavily doped to form a source/drain region by using the conductive layer, the first spacer, and the second spacer as a mask.

Abstract: A method of forming a barrier layer is disclosed. The barrier layer is formed on the upper surface of the tungsten plug. The method of forming the barrier layer is mainly a nitridation reaction. The nitridation reaction makes use of NH.sub.3 plasma, N.sub.2 plasma and N.sup.+ implantation.

Abstract: A method of fabricating a MOS FET is provided. An oxide layer and a polysilicon layer are successively formed on the semiconductor substrate. A pyramidical photoresist layer is used as a mask for forming a hat-shaped gate structure. A first ion implantation process is performed to form an LDD structure.

Abstract: An LDD source/drain region is manufactured adjacent a gate electrode using a single ion implantation step. The method begins by providing a polysilicon gate electrode on a gate oxide over a substrate and then providing a thin, layer of CVD oxide over the gate electrode and over the substrate. A thicker, second layer of a material different from the first silicon oxide layer is deposited over the device and is etched back to form sidewall spacer structures alongside and spaced slightly from the gate electrode. The spacer structures formed from the second layer are then used as a mask to etch the oxide layer where it is exposed over the active regions of the substrate and then the spacer structures are removed. The portion of the oxide layer that remains over the top and sides of the gate electrode and over portions of the substrate adjacent the gate electrode is then used as a mask for an ion implantation process.

Abstract: A process of fabricating metal gate electrodes for MOS transistors included in semiconductor IC devices is disclosed. The process includes first providing a silicon substrate having formed over the surface thereof the field oxide layers and a gate dielectric layer defined in the transistor active region. A thin layer of silicon is then formed over the surface of the gate dielectric layer. A metal layer is then deposited over the surface of the gate dielectric layer by performing an LPCVD procedure in a gaseous environment containing silane and tungsten fluoride. The LPCVD procedure deposits tungsten over the surface of the silicon layer by reducing the tungsten fluoride into tungsten atoms while consuming the thin silicon layer to exhaustion. The gate structure in the active region is then formed by patterning in the metal layer, and the gate structure includes the metal gate electrode layer and the gate dielectric layer.

Abstract: A method of improving hot carrier degradation comprises a silicon substrate on which an isolation oxide layer is formed to define an active region. The active region comprises a gate including a gate oxide layer. A thin oxide layer is formed over the gate, the isolation oxide layer, and the silicon substrate. With a tilt angle, a nitrogen ion is implanted into the interface between the gate and the silicon substrate at a corner. The gate oxide layer is thus nitridized. After a spacer around the gate is formed, a post heat annealing is performed. Using nitrogen ion implantation with a wide angle, the hot carrier degradation can be improved, and the reliability of gate oxide layer is enhanced.

Abstract: A method of fabricating a metal-oxide semiconductor (MOS) transistor is provided. This method is devised particularly to reduce the level of degradation to the MOS transistor caused by hot carriers. In the fabrication process, a plasma treatment is applied to the wafer to as to cause the forming of a thin layer of silicon nitride on the wafer which covers the gate and the lightly-doped diffusion (LDD) regions on the source/drain regions of the MOS transistor. This thin layer of silicon nitride acts as a barrier which prevents hot carriers from crossing the gate dielectric layer, such that the degradation of the MOS transistor due to hot carriers crossing the gate dielectric layer can be greatly minimized.

Abstract: A method of forming MOS components provides that after the formation of the gate and the doped source/drain regions, a polysilicon layer is deposited and planarized using a chemical-mechanical polishing method. The resulting unremoved polysilicon layer acts as source/drain terminals. Through these arrangements, the ion doped source/drain regions will have shallow junctions, yet their junction integrity will not be compromised by subsequent contact window etching and metallization processes. Furthermore, the front-end processes for forming the MOS component provide a good planar surface that offers great convenience for the performance of subsequent back-end processes.

Abstract: The present invention relates to a method of forming lightly doped drains in metallic oxide semiconductor (MOS) components. The method includes forming a first, second, and third insulating layer above a silicon substrate having a gate, etching back the layers to leave behind L-shaped first spacers on sidewalls of the gate, followed by doping second type ions into the silicon substrate to form first lightly doped drains in the silicon substrate surface below the L-shaped first spacers, and second lightly doped drains in the silicon substrate surface elsewhere, further forming a fourth insulating to form third spacers, and using the using the third spacers, the first insulating layer, and the gate as masks when doping second type ions into the silicon substrate so as to form source/drain regions in silicon substrate surfaces not covered by the third spacers. Such a method produces greater yield and reduces leakage current from the transistor components.

Abstract: A method for cleaning a substrate prior to tungsten deposition is disclosed, said substrate having via holes and trenches lines thereon. The method includes steps ofproviding a solution of hydroxylamine sulfate; dipping said substrate in said solution; and agitating said solution by an agitating device.