Abstract: A method for forming doped p-type gate is disclosed as the following description. The method includes that, firstly, a semiconductor substrate is provided. The semiconductor substrate is etched to form a concave portion as a shallow trench isolation. A first silicon dioxide is filled into the shallow trench isolation. A n-type well is formed into the semiconductor substrate. A silicon germanium layer, named as the doped p-type layer is formed on the surface of semiconductor substrate and the surface of shallow trench isolation. A silicon nitride layer, named as the anti-reflection layer is formed on the surface of silicon germanium layer. The portions of silicon nitride layer and the portions of silicon germanium layer are etched as a gate region. The source/drain extension is formed. A second silicon dioxide layer is deposited over the surface of semiconductor substrate and the surface of nitride layer. The second silicon dioxide layer is etched as a spacer beside the sidewall of gate region.

Abstract: An electrostatic discharge protection apparatus with silicon control rectifier and the method of fabricating the apparatus. Using silicon on insulator technique, a bottom layer, a P-well, a first source/drain region, a second source/drain region and a gate are formed. A selective epitaxial growth region is selectively formed on the first source/drain region, and an N+ region is formed on the bottom layer. The lower portion of the N+ region is then adjacent to the P-well, and the upper portion of the N+ region is adjacent to the gate. Thus, a PNPN silicon control rectifier is formed, and the silicon on insulation CMOS technique is effectively transplanted into the electrostatic discharge apparatus.

Abstract: A method for forming semiconductor devices is disclosed. The method of the present invention includes providing a semiconductor substrate, followed by forming shallow trench isolation (STI) process, and then a dummy gate is formed by silicon nitride layer which is deposited and defined. With appropriate wet etching, this dummy poly can be removed. After local punch-through implantation, reverse offset spacer is formed to reduce Cgd (capacitance is between gate and drain) and poly-CD (critical dimension). Polysilicon is deposited followed by polysilicon CMP. After thick Ti-salicidation, the usual CMOS (Complementary Metal-Oxide-Semiconductor) processes are proceeded.

Abstract: An SOI layer has a dielectric layer and a silicon layer formed on the dielectric layer. A shallow trench isolation structure is formed on the silicon layer. The STI structure passes through to the dielectric layer. A thermal diffusion process is performed to drive dopants into a first region of the silicon layer so as to form an N-well or P-well doped region. Next, a thermal diffusion process is performed to drive dopants into a second region of the silicon layer so as to form a P-well or N-well doped region. Finally, an epitaxy layer, having a thickness of about 200 angstroms, is grown on the surface of the silicon layer by way of a molecular-beam epitaxy (MBE) growth process, a liquid-phase epitaxy (LPE) growth process, or a vapor-phase epitaxy (VPE) growth process.

Abstract: A copper fuse structure for integrated circuit employs two copper pads formed over a semiconductor substrate. The two copper pads are electrically insulated by dielectrics. An aluminum line is utilized to cover and electrically connect the two copper pads.

Abstract: A method for forming semiconductor devices is disclosed. The method of the present invention includes providing a semiconductor substrate, followed by forming shallow trench isolation (STI) process, and then a dummy gate is formed by silicon nitride layer which is deposited and defined. With appropriate wet etching, this dummy poly can be removed. After local punch-through implantation, reverse offset spacer is formed to reduce Cgd (capacitance is between gate and drain) and poly-CD (critical dimension). Polysilicon is deposited followed by polysilicon CMP. After thick Ti-salicidation, the usual CMOS (Complementary Metal-Oxide-Semiconductor) processes are proceeded.

Abstract: An ESD protection structure having sided single crystal Si junction diode for protecting an internal circuit. The ESD protection structure is electrically coupled between an input pad and a node, and the internal circuit is electrically coupled to the node. The ESD protection structure includes at least a single crystal Si resistor, which is formed over an insulating material layer and electrically coupled between the input pad and the node. The ESD protection structure further includes at least a single crystal Si-sided junction diode, which is formed over the insulating material layer and electrically coupled between one terminal of corresponding power supply and the node.

Abstract: A self-aligned contact process. A substrate is provided. A gate including a polysilicon layer and a metal silicide layer is formed on the substrate. A cap layer is formed on the gate to protect the gate. A first spacer is formed on the sidewall of the gate. A first ion implantation is performed using the gate and the first spacer as a first mask to form lightly doped regions in the substrate. A conformal liner layer is formed on the cap layer, the first spacer and the substrate. An insulating layer is formed on the conformal liner layer. A part of the insulating layer and a part of the liner layer are removed until exposing the cap layer. A part of the liner layer remaining on the first spacer and a part of the insulating layer remaining on the remaining liner layer are used as a second spacer. A second ion implantation is performed to form source/drain regions with lightly doped drain (LDD) structures in the substrate beside the second spacer.

Abstract: A structure of combined passive elements and logic circuits on a SOI (Silicon On Insulator) wafer. By combining passive elements (including a resistor, an inductor and a capacitor) with a logic device on a SOI wafer with dual damascene technology, an extremely thick inductor that effectively reduces the resistance of the inductor can be formed while also reducing the layout area. The invention is compatible with conventional VLSI technology without increasing number of masks or process steps. Furthermore, because the resistor of the invention is composed of single crystal Si, the resistor has high stability and low noise. Therefore, the structure according to the invention is suitable for RF device design and is also suitable for a System On Chip design.

Abstract: A method for forming combining a logic circuit and a capacitor of a passive element is disclosed. The method includes the following steps. First, a semiconductor wafer having a first dielectric layer and a first contact is provided. A first metal layer is formed on the first contact and around an estimated area. A second dielectric layer is formed on the first metal layer and the first dielectric layer. The second dielectric layer is formed on the first metal layer and the first dielectric layer. The second metal is formed on areas of the metal layer of the estimated areas. The third dielectric layer is formed on the second metal layer and the second dielectric layer. The fourth dielectric layer is formed on the third dielectric layer. The fifth dielectric layer is formed on the fourth dielectric layer. Sequentially the fifth dielectric layer, the fourth dielectric layer, the third dielectric layer, and the second dielectric layer are all etched.

Abstract: A method for forming a MOS transistor is provided. A gate oxide layer, a polysilicon layer, a barrier layer and a conductive layer are sequentially formed on a provided substrate. A photolithography and etching process is carried out to remove a portion of the conductive layer and a portion of the barrier layer until exposing the polysilicon layer. An ion implantation is performed to form lightly doped regions in the substrate using the remaining conductive layer and the remaining barrier layer as a mask. A spacer is formed on the side-wall of the conductive layer and on the side-wall of the barrier layer. The polysilicon layer and the gate oxide layer, which are in positions other than those of the remaining conductive layer and the spacer, are removed. The remaining conductive layer and the remaining polysilicon layer constitute a gate with an inversed, T-shaped cross-section.

Abstract: A method of suppressing junction capacitance of the source/drain regions is disclosed in this invention. The source/drain regions are formed by double implantation of phosphorus ions and arsenic ions. The phosphorus ion implantation lowers the energy needed in the implantation of arsenic ions, and reduces dislocations in the source/drain regions formed during implanting arsenic ions. Further, the double implantation suppresses the junction profile of arsenic ions, and enhances the width of depletion regions. So, the junction capacitance is reduced, thereby accelerate the function of semiconductor devices.

Abstract: A method for fabricating a metal-oxide semiconductor (MOS) transistor. A substrate having a gate structure is provided. The method of the invention includes forming a liner spacer on each side of the gate structure and a low dopant density region deep inside the substrate. The low dopant density region has a lower dopant density than that of a lightly doped region of the MOS transistor. Then a interchangeable source/drain region with a lightly doped drain (LDD) structure and an anti-punch-through region is formed on each side of the gate structure in the low dopant density region. The depth of the interchangeable source/drain region is not necessary to be shallow.

Abstract: A method for forming a gate that improves the quality of the gate includes sequentially forming a gate oxide layer, a polysilicon layer, a conductive layer and a masking layer on a substrate. Thereafter, the masking layer, the conductive layer, the polysilicon layer and the gate oxide layer are patterned to form the gate. Then, a passivation layer, for increasing the thermal stability and the chemical stability of the gate, is formed on the sidewall of the conductive layer by ion implantation with nitrogen cations. The nitrogen cations are doped into the substrate, under the gate oxide layer, by ion implantation, which can improve the penetration of the phosphorus ions.

Abstract: A method for manufacturing a gate terminal comprising the steps of providing a substrate, then forming and patterning an oxide layer to form a gate region. Next, a gate oxide layer and a crystalline silicon layer are formed in the gate region. This is followed by depositing a tungsten layer in the gate region, and then polishing the tungsten layer to form a final tungsten layer functioning as the gate electrode. Finally, the oxide layer is removed. The method of this invention is able to control the dimensions of the gate terminal produced. Moreover, the formation of a thin crystalline silicon layer over the gate oxide layer helps to increase the bonding strength with the metallic layer, and that the gate electrode can be formed at a lower processing temperature. Therefore, the gate so formed has a higher quality and the processing of the semiconductor is much easier. Furthermore, the silicon nitride layer can serve as an etching stop layer during the etching operation of the oxide layer.

Abstract: A method for forming inter-metal dielectric is disclosed. The method normally includes the following steps. First of all, a semiconductor wafer is provided. Then, forming a first metal layer on a portion of the substrate is carried out. A first dielectric layer is formed on the first metal layer and the substrate. Consequentially a tantalum nitride layer is formed on the first dielectric layer. A first photoresist layer can be formed on the tantalum nitride layer, especially first photoresist layer has a first pattern defining a trench area located over the first metal layer, and has a second pattern defining an etch stop area. The tantalum nitride layer will be etched by the first photoresist layer. A second dielectric layer is formed over the etched tantalum nitride layer and the first dielectric layer.

Abstract: A method for fabricating a metal-oxide semiconductor (MOS) transistor is provided. The method has steps of sequentially forming an oxide layer, a polysilicon layer and a cap layer on a semiconductor substrate to form a first-stage gate. An interchangeable source/drain region with a lightly doped drain (LDD) structure is formed in the substrate at each side of the first-stage gate. An insulating layer is formed over the substrate, and is planarized so as to exposed the cap layer. Removing the exposed cap layer forms an opening that exposes the polysilicon layer. Using the insulating layer as a mask, a self-aligned selective local implantation process is performed to form a threshold-voltage doped region and an anti-punch-through doped region below the oxide layer in the substrate. A conductive layer is formed over the substrate to fill the opening.

Abstract: A new improvement for selective epitaxial growth is disclosed. In one embodiment, the present invention provides a low power metal oxide semiconductor field effect transistor (MOSFET), which includes a substrate. Next, a gate oxide layer is formed on the substrate. Moreover, a polysilicon layer is deposited on the gate oxide layer. Patterning to etch the polysilicon layer and the gate oxide layer to define a gate. First ions are implanted into the substrate by using said gate as a hard mask. Sequentially, a liner oxide is covered over the entire exposed surface of the resulting structure. Moreover, a conformal first dielectric layer and second dielectric layer are deposited above the liner oxide in proper order. The second dielectric layer is etched back to form a dielectric spacer on sidewall of the first dielectric layer.

Abstract: A method for manufacturing MOS device that utilizes a special shape spacer as a mask in an ion implantation operation to form a graded source/drain region. The special shaped spacer has a thin wall section on the far side away from the gate so that as ions are implanted into the substrate to form a source/drain region, dopants are implanted to various depths. The graded doping profile in the source/drain region not only reduces the severity of short channel effects, but also forms a base for forming an integral junction over the source/drain region in subsequent self-aligned silicide process.

Abstract: The process includes the following steps. At first, a masking layer is formed over the semiconductor substrate. A portion of the masking layer is then removed to form an opening to the semiconductor substrate. Sidewall spacers are formed on the opening and a portion of the semiconductor substrate is removed to form a trench, through an aperture defined by the sidewall spacers. The sidewall spacers is then removed and a liner layer is formed conformably over the trench.