Abstract: An image sensor multi-chips package structure, includes a first package comprising a first chip with image sensors having first bonding pads and micro lens on a first active surface, a first die receiving window and first conductive inter-connecting through holes penetrated from a first upper contact pads on a first upper surface of the first chip to a first lower contact pads on a first lower surface of the first chip, wherein a first upper build up layer on the active surface of the first chip coupling from the first bonding pads to the first upper contact pads; a second package comprising a second chip having second bonding pads on a second active surface, a second die receiving window and second conductive inter-connecting through holes penetrated from a second upper contact pads of a second upper surface of the second chip to a second lower contact pads on a second lower surface of the second chip, wherein a second upper build up layers on the second upper surface for coupling from the second bonding pad

Abstract: The present invention provides a structure of multi-chips package comprising: a substrate with a die receiving cavity formed within an upper surface of the substrate and a first through holes structure, wherein terminal pads are formed under the first through holes structure. A first die is disposed within the die receiving cavity and a first dielectric layer is formed on the first die and the substrate. A first re-distribution conductive layer (RDL) is formed on the first dielectric layer. A second dielectric layer is formed over the first RDL. A third dielectric layer is formed under a second die. A second re-distribution conductive layer (RDL) is formed under the third dielectric layer. A fourth dielectric layer is formed under the second RDL. Conductive bumps are coupled to the first RDL and the second RDL. A surrounding material surrounds the second die. The second die is coupled to the first die through the first RDL, second RDL and the conductive bumps.

Abstract: The present invention discloses a structure of package comprising: a substrate with a die receiving through hole; a base attached on a lower surface of the substrate; a die disposed within the die receiving through hole and attached on the base; a dielectric layer formed on the die and the substrate; a re-distribution layer (RDL) formed on the dielectric layer and coupled to the die; a protection layer formed over the RDL; and pluralities of pads formed on the protection layer and coupled to the RDL. The RDL is made from an alloy comprising Ti/Cu/Au alloy or Ti/Cu/Ni/Au alloy.

Abstract: The present invention discloses a super thin chip scale package structure and method of the same. The super thin chip scale package structure comprises a substrate, a wafer with a plurality of die having a plurality of bonding pads, a first dielectric layer, a via conductive layer, a second dielectric layer, a redistribution layer trace and soldering bumps formed on the wafer in sequence. Due to minimizing the sizes of the package structure, the present invention can provides a super thin chip scale package structure. Especially, the method for manufacturing the super thin chip scale package comprises sawing the wafer and back-lapping the back side of the wafer and etching the back side of the substrate to provide the super thin chip scale package structure. Accordingly, the present invention can minimize the size of the package structure, and improve the manufacturing process effectively.

Abstract: The present invention discloses a structure of package comprising: a substrate with a die receiving through holes, a conductive connecting through holes structure and coupled a first contact pad on the upper surface of the substrate and a second contact pads on lower surface of the substrate; at least a die with metal pads disposed within the die receiving through holes; a surrounding material formed under the die and filled in the gap between the sidewall of die and sidewall of the die receiving though holes; a re-distribution layer (RDL) formed on the die, substrate and surrounding material; and coupled the metal pads of the die to the first contact pad; an isolating base having adhesion material formed over the RDL.

Abstract: The present invention discloses a structure of package comprising: a substrate with die receiving through holes, conductive connecting through holes and contact metal pads; a base attached on a portion of the lower surface of the substrate; multiple dice disposed within the die receiving through holes and attached on the base; multiple dielectric layers formed on the multiple dice and the substrate; multiple re-distribution layers (RDL) formed within the multiple dielectric layers and coupled to the multiple dice; a top layer formed over the RDL; and pluralities of terminal pads formed on the backside of the substrate and coupled to the RDL through the connecting through holes. The RDL is made from an alloy comprising Ti/Cu/Au alloy or Ti/Cu/Ni/Au alloy.

Abstract: The present invention discloses a structure of package comprising: a substrate with a die receiving through hole; a base attached on a lower surface of the substrate; a die disposed within the die receiving through hole and attached on the base; a dielectric layer formed on the die and the substrate; a re-distribution layer (RDL) formed on the dielectric layer and coupled to the die; a protection layer formed over the RDL; and pluralities of pads formed on the protection layer and coupled to the RDL. The RDL is made from an alloy comprising Ti/Cu/Au alloy or Ti/Cu/Ni/Au alloy.

Abstract: The present invention provides a semiconductor device package having pseudo chips structure comprising a first substrate with die receiving through holes formed thereon; a first die having first bonding pads and a second die having second bonding pads disposed within the die receiving through holes, respectively; an adhesion material formed in the gap between the first and second die and sidewalls of the die receiving though holes of the first substrate; redistribution lines formed to couple the first contact pads formed on the first substrate to the first bonding pads and the second bonding pads, respectively; and a protection layer formed on the redistribution lines, the first die, the second die and the first substrate.

Abstract: A package on package structure for semiconductor devices comprises at least one first level package having at least first level semiconductor die therein, wherein the package having first level contact pads formed on a first upper and lower surfaces of the first level package, the first level package having a first level upper build up layers and/or a first level lower build up layer to couple to bonding pads of the first level semiconductor die to contact first level pads on the both upper and lower surfaces of the first level package; a second level package having at least one second semiconductor die contained therein, wherein the second level package has a second level contact pads on a second upper and lower surfaces of the second level package, and conductive connecting through holes; wherein the second level package have a second level upper build up layer and/or second level lower build up layer to couple second level bonding pads of the second semiconductor die to contact second level pads and the co

Abstract: The present invention discloses a structure of package comprising: a substrate with a die receiving through hole, a connecting through hole structure and a first contact pad; a die disposed within the die receiving through hole; a surrounding material formed under the die and filled in the gap between the die and sidewall of the die receiving though hole; a dielectric layer formed on the die and the substrate; a re-distribution layer (RDL) formed on the dielectric layer and coupled to the first contact pad; a protection layer formed over the RDL; and a second contact pad formed at the lower surface of the substrate and under the connecting through hole structure.

Abstract: The present invention provides a structure of elastic dielectric layers with certain through holes adjacent to the angle of a RDL of WLP to absorb the stress. The elastic dielectric layer is made from silicone based materials with specific range of CTE, elongation rate and hardness, which can improve the mechanical reliability of the structure during temperature cycling test. The CTE difference between the RDL and the elastic dielectric material still may cause the elastic dielectric layer crack; to solve this problem, The present invention further provides a structure of dielectric layers with certain open through holes adjacent to the curve portion of a RDL of WLP which can reduce the stress accumulated at area of the dielectric layer adjacent to the RDL/dielectric layer interface to solve the crack problem of the dielectric layer.

Abstract: The present invention provides a structure of package comprising a substrate with a pre-formed die receiving cavity formed and/or terminal contact metal pads formed within an upper surface of the substrate. A die is disposed within the die receiving cavity by adhesion and a dielectric layer formed on the die and the substrate. At least one re-distribution built up layer (RDL) is formed on the dielectric layer and coupled to the die via contact pad. Connecting structure, for example, UBM is formed over the redistribution built up layer. Terminal Conductive bumps are coupled to the UBM.

Abstract: The present invention discloses a tool structure for chip redistribution and method of chip redistribution. The tool structure comprises a base substrate, a separable adhesion film formed on the base substrate, and the patterned glues placed on the separable adhesion film for fixating the dice covered by the core paste materials formed on a fixed substrate. The fixed substrate is bonding on the core paste materials and dice to form the panel wafer. The method comprises printing the pluralities of patterned glues placed on the separable adhesion film and the bonding pluralities of dice covered by the core paste materials, and then, the fixed substrate is bonding on the core paste materials and pluralities of dice. The method further comprises curing and separating the glues and the pluralities of dice with the fixed substrate, and then cleaning the residual glues on the panel wafer (pluralities of dice).

Abstract: The present invention proposes a 3D electronic packaging structure with enhanced grounding performance and embedded antenna, and the packaging unit can achieve multi-chip stacking through the signal contacts on the top and bottom surfaces of the unit. A single or multiple grounding layers are on the back of the substrate in the packaging unit to facilitate the grounding for the semiconductor element; further, the packaging unit is applicable to a wafer level packaging process, so the manufacturing cost of each individual packaging unit is reduced. The above grounding layers are also the signal transmission paths of the electronic elements in the packaging structure of the invention, and a single or multiple via holes around the electronic element layers allow electrical signal connection between the top and bottom surfaces of the packaging structure, and thus enable more functionality in the packaging unit.

Abstract: The present invention provides an image sensor module. The image sensor module has a die formed on a substrate, the die having a micro lens area, a lens holder formed on the substrate and over the die, a lens formed in the lens holder. A filter is formed within the lens holder and between the lens and the die, and at least one passive device formed on the substrate and covered within the lens holder. Conductive bumps or LGA (leadless grid array) are formed on the bottom surface of the substrate.

Abstract: An image sensor package comprises a substrate, a chip mounted over the substrate, A molding material is formed surrounding the chip to expose a micron lens area, wherein the molding material includes via structure passing there through. A protection layer is formed on the micro lens area to prevent the micro lens. A redistributed conductive layer is formed over the molding material to connect to a pad of the chip. Metal pads are formed on via structure as connecting points with PCB. A cover layer is formed over the substrate to isolate the metal pads.

Abstract: The present invention provides a structure of multi-chips package comprising: a substrate with a die receiving cavity formed within an upper surface of the substrate and a first through holes structure, wherein a terminal pads is formed under the first through holes structure. A first die is disposed within the die receiving cavity and a first dielectric layer is formed on the first die and the substrate. A first re-distribution conductive layer (RDL) is formed on the first dielectric layer. A second dielectric layer is formed over the first RDL and a second die is attached on the second dielectric layer. A surrounding material surrounds the second die. A third dielectric layer is formed over the second die and the surrounding material. A second re-distribution conductive layer (RDL) is formed on the third dielectric layer. A protection layer is formed over the second RDL.

Abstract: To pick and place standard first chip size package on a base with a second chip for obtaining an appropriate stacking chip size package than the original chip size package. The package structure has a larger chip size package than the size of the traditional stacking package. Moreover, the terminal pins of the flip chip package may be located on peripheral of LGA package or on array of BGA package.

Abstract: A wafer level package comprises a wafer having a plurality of dice formed thereon; a thinner metal cover with a cavity formed therein attached on the wafer by an adhesive material to improve thermal conductivity of the package. A protection film is formed on back side of the metal cover and filled into the cavity, thereby facilitating for laser marking and obtaining a better sawing quality of the package.

Abstract: The present invention provides a structure for etching process. The structure has a mask for protecting an area of a wafer from being etched and a seal ring attached under a lower surface of the mask. The mask has at least one air opening to expose an area to be etched. Furthermore, the mask is attached on the wafer through the seal ring. In addition, the present invention provides also a method to form a mask for dry etching process. First, the present invention includes a step of providing a base material and coating the masking material on both sides of the base material. The next step is to pattern the masking material to form openings. Subsequently, the base material is etched through the openings to create at least one mask opening and a mask cavity. Finally, removing the mask material is performed.