Abstract: An image sensor die comprises a substrate and an image sensor array formed over the substrate. Micro lens are disposed on the image sensor array. A protection layer is formed on the micro lens to prevent the micro lens from particle containment.

Abstract: The present invention discloses a structure of wafer level packaging. The structure comprises a first patterned isolation layer, a conductive layer and a second patterned isolation layer. The first patterned isolation layer is formed with a passivation layer of an IC (Integrated Circuit). The conductive layer is configured to have a curved or winding conductive pattern. The second patterned isolation layer is formed over the conductive layer to have a plurality of openings, and contact metal balls can be formed on the openings to electrically couple to a print circuit board.

Abstract: The present invention discloses a structure of package. The structure comprises a flip chip solder bumping structure, having a plurality of chips and solder bumps. A substrate has a plurality of conductive lines electrically coupling with the plurality of solder bumps. A print circuit board has a plurality of solder balls electrically coupling with the plurality of conductive lines.

Abstract: The present invention discloses an image sensor module and forming method of wafer level package. The image sensor module comprises an isolating base, a wafer level package, a lens holder, and a F.P.C.. The wafer level package having a plurality of image sensor dies and a plurality of solder balls is attached to the isolating base. A plurality of lens are placed in the lens holder, and the lens holder is located on the image sensor dies. The lens holder is placed in the F.P.C., and the F.P.C. has a plurality of solder joints coupled to the solder balls for conveniently transmitting signal of the image sensor dies. Moreover, the image sensor dies may be packaged with passive components or other dies with a side by side structure or a stacking structure.

Abstract: To pick and place standard dies on a new base for obtaining an appropriate and wider distance between dies than the original distance of dies on a wafer. The package structure has a larger size of balls array than the size of the die by fan out type package. Moreover, the die may be packaged with passive components or other dies with a side by side structure or a stacking structure .

Abstract: The present invention discloses a contact structure and method for burn-in testing. The structure comprises a print circuit board, metal solder join fixed to the print circuit board, and contact fixed plate. The contact metal springs are located on the metal solder join and contacted with contact metal balls. The metal solder join is located on the contact fixed plate. Between the contact metal balls and the contact metal springs keep an approximately constant pressure and self-alignment by using the surface of the fixed plate contacting with the surface of the ball grid array (BGA) package.

Abstract: To pick and place standard dies on a new base for obtaining an appropriate and wider distance between dies than the original distance of dies on a wafer. The package structure has a larger size of balls array than the size of the die by fan out type package. Moreover, the die may be packaged with passive components or other dies with a side by side structure or a stacking structure.

Abstract: The present invention provides a method for forming wafer level package. The wafer level package comprising: a plurality of dies formed on the wafer; an I/O metal pad formed on the first surface of the wafer; and coating a photo sensitive polymer, on the first surface of the wafer, then a portion of the film is removed by laser. In the next step, coating a first photoresist on the second surface of the wafer. Forming a first conductive layer in the opening of the photo sensitive polyimide and then covering a I/O metal pad. Next, forming a seeding layer with copper on the top of the first conductive layer and on the photo sensitive polymer; and forming a second photoresist on the seeding layer to define the circuit pattern diagram. Then, forming a second conductive layer to the circuit pattern diagram located on the defined area of the second photoresist.

Abstract: The present invention comprises a plurality of dies formed on the wafer and an I/O metal pad formed on the first surface of the wafer. Then, photo PI is coated on the first surface, then a portion of the PI is removed by laser. Next step, a first photoresist is coated on the second surface of the wafer and the photoresist includes positive photoresist. A first conductive layer is formed in the hole of the photo PI and covers a metal pad. Subsequently, a seeding layer with copper is formed on the top of the first conductive layer and the photo sensitive polymer layer. Then, a second photoresist is formed on the seeding layer to define the circuit pattern diagram. Then, a second cnductive layer is formed. Next step is to remove the second and the first photoresist covered by the second photoresist, thereby forming trenches therein. Then, the filling material is filled into the trench and covers the circuit pattern diagram.

Abstract: An integrated wafer level board/card assembly method combines wafer level packaging, testing and assembly process. The integrated process includes the steps of first wafer sorting, laser repairing, second wafer sorting, wafer level burn-in, wafer level packaging, final testing, wafer sawing and board/card assembly. Information including wafer mapping and yield data of a process step is used as the input data to a next process step. Burn-in circuits and internal probing pads are built in the dice of the wafer to enable wafer level burn-in. A wafer cassette is used to move wafers between steps. Probers are used as the primary equipment in many steps to provide automatic wafer loading and testing. A multi-chip module die bonder, an IR re-flow system and an open/short tester form an automatic in-line system to accomplish the step of assembling a plurality of integrated circuit chips on a PC board.

Abstract: The present invention comprises a plurality of dies formed on the wafer and an I/O metal pad formed on the first surface of the wafer. Then, photo PI is coated on the first surface, then a portion of the PI is removed by laser. Next step, a first photoresist is coated on the second surface of the wafer and the photoresist includes positive photoresist. A first conductive layer is formed in the hole of the photo PI and covers a metal pad. Subsequently, a seeding layer with copper is formed on the top of the first conductive layer and the photo sensitive polymer layer. Then, a second photoresist is formed on the seeding layer to define the circuit pattern diagram. Then, a second conductive layer is formed. Next step is to remove the second and the first photoresist covered by the second photoresist, thereby forming trenches therein. Then, the filling material is filled into the trench and covers the circuit pattern diagram.

Abstract: The present invention comprises a probe card having a cavity formed on the lower surface of the probe card. A buffer is formed in the cavity to act as cushion and a flexible circuit board is attached on the probe card surface that faces to the testing object. A probe is formed on the flexible circuit board, insulation material is formed on the flexible circuit board to fix the probe. Conductive material is coated on the probe to enhance the strength of the probe.

Abstract: A built-in circuit for wafer level burn-in of a die. The burn-in circuit includes a main burn-in control circuit, a word line control circuit and a bit line control circuit. A number of internal probing pads are also provided to receive voltages for stressing a gate oxide or capacitor oxide layer. A burn-in test system has a plurality of programmable power suppliers and programmable relays for providing control and power signals to a membrane or micro spring probe card used for the wafer level burn-in of multiple dice at the same time. Wafers are loaded and aligned in a prober with an automatic probing station and a hot chuck for the burn-in. The wafer level burn-in reduces the burn-in time of an integrated circuit chip from several days to several minutes.