Patents by Inventor Wen Kuo
Wen Kuo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240249961Abstract: The present disclosure relates to a method of programming an EFEM. The method includes placing an automatic teaching element within an EFEM chamber at a first time. The automatic teaching element is operated at a second time to measure one or more parameters corresponding to an initial position of an EFEM robot within the EFEM chamber. The automatic teaching element is removed from the EFEM chamber at a third time and then placed within the EFEM chamber at a fourth time. The automatic teaching element is operated at a fifth time to determine positional parameters describing a difference between the initial position and a new position of the EFEM robot. A second plurality of steps are determined based upon the positional parameters. The EFEM robot is configured to move along the second plurality of steps that extend along a path between first and second positions.Type: ApplicationFiled: April 3, 2024Publication date: July 25, 2024Inventors: Chien-Fa Lee, Hsu-Shui Liu, Jiun-Rong Pai, Shou-Wen Kuo
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Patent number: 12037687Abstract: A gas tube, a gas supply system containing the same and a semiconductor manufacturing method using the same are provided. The gas tube includes a porous material body and a resistant sheath surrounding the porous material body. The porous material body has a hollow tube structure and an empty cavity inside the hollow tube structure. The porous material body is hydrophobic and has a plurality of pores therein. The resistant sheath is disposed on the porous material body and surrounds the porous material body. The resistant sheath includes a plurality of holes penetrating through the resistant sheath.Type: GrantFiled: June 29, 2022Date of Patent: July 16, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-Shiung Chen, Cheng-Yi Huang, Chih-Shen Yang, Shou-Wen Kuo, Po-Wen Chai
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Patent number: 12020962Abstract: The present disclosure provides a measuring system. The measuring system includes an insulative tube, a capacitor and a static charge meter. The insulative tube is configured to allow a fluid to flow therethrough. The capacitor is disposed on a surface of a section of the insulative tube. The capacitor includes a first metallic layer, a second metallic layer opposite to the first metallic layer, and a dielectric layer sandwiched between the first metallic layer and the second metallic layer. The static charge meter is electrically coupled to the capacitor and configured to measure static charge accumulated inside the section of the insulative tube.Type: GrantFiled: August 30, 2021Date of Patent: June 25, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Tzu-Sou Chuang, Chwen Yu, En Tian Lin, Chi Wen Kuo
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Publication number: 20240189961Abstract: A slurry monitoring device, a CMP system and a method of in-line monitoring a slurry are provided. The slurry monitoring device incudes a slurry metrology cell, a plurality of light sources, at least one optical lens, and at least one optical detector. The slurry metrology cell accommodates a slurry. The light sources emit light beams on the slurry in the slurry metrology cell. The at least one optical lens is disposed between the plurality of light sources and the slurry metrology cell. The at least one optical lens modifies a size of a light spot of the light beams impinged on the slurry. The at least one optical detector detects an intensity of the light beams scattered by abrasive particles in the slurry.Type: ApplicationFiled: February 21, 2024Publication date: June 13, 2024Inventors: CHWEN YU, TING-WEN CHEN, CHI WEN KUO
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Publication number: 20240186162Abstract: An apparatus for inspecting wafer carriers is disclosed. In one example, the apparatus includes: a housing; a load port; a robot arm inside the housing; and a processor. The load port is configured to load a wafer carrier into the housing. The robot arm is configured to move a first camera connected to the robot arm. The first camera is configured to capture a plurality of images of the wafer carrier. The processor is configured to process the plurality of images to inspect the wafer carrier.Type: ApplicationFiled: February 16, 2024Publication date: June 6, 2024Inventors: Cheng-Kang HU, Shou-Wen KUO, Sheng-Hsiang CHUANG, Jiun-Rong PAI, Hsu-Shui LIU
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Publication number: 20240170339Abstract: In a method of manufacturing a semiconductor device, an n-type source/drain epitaxial layer and a p-type source/drain epitaxial layer respectively formed, a dielectric layer is formed over the n-type source/drain epitaxial layer and the p-type source/drain epitaxial layer, a first opening is formed in the dielectric layer to expose a part of the n-type source/drain epitaxial layer and a second opening is formed in the dielectric layer to expose a part of the p-type source/drain epitaxial layer, and the n-type source/drain epitaxial layer and the p-type source/drain epitaxial layer respectively recessed. A recessing amount of the n-type source/drain epitaxial layer is different from a recessing amount of the p-type source/drain epitaxial layer.Type: ApplicationFiled: March 2, 2023Publication date: May 23, 2024Inventors: Te-Chih Hsiung, Yun-Hua Chen, Yang-Cheng Wu, Sheng-Hsun Fu, Wen-Kuo Hsieh, Chih-Yuan Ting, Huan-Just Lin, Bing-Sian Wu, Yi-Hsuan Chiu
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Patent number: 11984331Abstract: The present disclosure relates to an equipment front end module (EFEM) teaching element. The EFEM teaching element includes a memory element configured to store data describing an initial position of an EFEM robot within an EFEM chamber. A position measurement device is configured to take measurements describing a new position of the EFEM robot within the EFEM chamber that is different than the initial position of the EFEM robot. A controller is configured to determine a set of new movement commands describing a path of the EFEM robot based upon the data describing the initial position of the EFEM robot and the measurements.Type: GrantFiled: October 28, 2020Date of Patent: May 14, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chien-Fa Lee, Hsu-Shui Liu, Jiun-Rong Pai, Shou-Wen Kuo
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Patent number: 11971859Abstract: Techniques are provided for implementing a defragmentation process during a merge operation performed by a re-compaction process upon a log structured merge tree. The log structured merge tree is used to store keys of key-value pairs within a key-value store. As the log structured merge tree fills with keys over time, the re-compaction process is performed to merge keys down to lower levels of the log structured merge tree to re-compact the keys. Re-compaction can result in fragmentation because there is a lack of spatial locality of where the re-compaction operations re-writes the keys within storage. Fragmentation increases read and write amplification when accessing the keys stored in different locations within the storage. Accordingly, the defragmentation process is performed during a last merge operation of the re-compaction process in order to store keys together within the storage, thus reducing read and write amplification when accessing the keys.Type: GrantFiled: April 28, 2022Date of Patent: April 30, 2024Assignee: NetApp, Inc.Inventors: Anil Paul Thoppil, Wei Sun, Meera Odugoudar, Szu-Wen Kuo, Santhosh Selvaraj
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Patent number: 11960453Abstract: Asynchronous snapshot invalidation techniques are described. According to various such techniques, an enhanced file handle structure may be defined that includes a snapshot generation ID that is to comprise a value that singularly identifies a snapshot performed at a particular point in time. In some embodiments, when a snapshot ID assigned to that snapshot is reused at a subsequent point in time, a different snapshot generation ID may be assigned to that subsequent snapshot. With respect to an in-core cache, the differing snapshot generation IDs may eliminate unacceptable ambiguity regarding respective file information sets corresponding to the initial and subsequent snapshots sharing the same snapshot ID. As a result, obsolete file information sets may be cleared from the in-core cache asynchronously, enabling improved performance. The embodiments are not limited in this context.Type: GrantFiled: February 28, 2023Date of Patent: April 16, 2024Assignee: NetApp, Inc.Inventors: Mardiros Z. Chakalian, Amber Palekar, Szu-Wen Kuo, Stephen Wu
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Patent number: 11961770Abstract: Some embodiments of the present disclosure relate to a processing tool. The tool includes a housing enclosing a processing chamber, and an input/output port configured to pass a wafer through the housing into and out of the processing chamber. A back-side macro-inspection system is arranged within the processing chamber and is configured to image a back side of the wafer. A front-side macro-inspection system is arranged within the processing chamber and is configured to image a front side of the wafer according to a first image resolution. A front-side micro-inspection system is arranged within the processing chamber and is configured to image the front side of the wafer according to a second image resolution which is higher than the first image resolution.Type: GrantFiled: November 4, 2021Date of Patent: April 16, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Han Lin, Chien-Fa Lee, Hsu-Shui Liu, Jiun-Rong Pai, Sheng-Hsiang Chuang, Surendra Kumar Soni, Shou-Wen Kuo, Wu-An Weng, Gary Tsai, Chien-Ko Liao, Ya Hsun Hsueh, Becky Liao, Ethan Yu, Ming-Chi Tsai, Kuo-Yi Liu
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Publication number: 20240120203Abstract: A method includes forming a dummy gate over a semiconductor fin; forming a source/drain epitaxial structure over the semiconductor fin and adjacent to the dummy gate; depositing an interlayer dielectric (ILD) layer to cover the source/drain epitaxial structure; replacing the dummy gate with a gate structure; forming a dielectric structure to cut the gate structure, wherein a portion of the dielectric structure is embedded in the ILD layer; recessing the portion of the dielectric structure embedded in the ILD layer; after recessing the portion of the dielectric structure, removing a portion of the ILD layer over the source/drain epitaxial structure; and forming a source/drain contact in the ILD layer and in contact with the portion of the dielectric structure.Type: ApplicationFiled: March 8, 2023Publication date: April 11, 2024Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Te-Chih HSIUNG, Yun-Hua CHEN, Bing-Sian WU, Yi-Hsuan CHIU, Yu-Wei CHANG, Wen-Kuo HSIEH, Chih-Yuan TING, Huan-Just LIN
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Patent number: 11938586Abstract: A slurry monitoring device, a CMP system and a method of in-line monitoring a slurry are provided. The slurry monitoring device incudes a slurry metrology cell, a plurality of light sources and at least one optical detector. The slurry metrology cell is configured to accommodating a slurry. The light sources are configured to emit light beams on the slurry in the slurry metrology cell. The light sources include a first light source configured to emit a first light beam having a first wavelength, and a second light source configured to emit a second light beam having a second wavelength longer than the first wavelength. The at least one optical detector is configured to detect an intensity of the light beams scattered by abrasive particles in the slurry.Type: GrantFiled: August 27, 2021Date of Patent: March 26, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Chwen Yu, Ting-Wen Chen, Chi Wen Kuo
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Patent number: 11929271Abstract: An apparatus for inspecting wafer carriers is disclosed. In one example, the apparatus includes: a housing; a load port; a robot arm inside the housing; and a processor. The load port is configured to load a wafer carrier into the housing. The robot arm is configured to move a first camera connected to the robot arm. The first camera is configured to capture a plurality of images of the wafer carrier. The processor is configured to process the plurality of images to inspect the wafer carrier.Type: GrantFiled: July 13, 2020Date of Patent: March 12, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Cheng-Kang Hu, Shou-Wen Kuo, Sheng-Hsiang Chuang, Jiun-Rong Pai, Hsu-Shui Liu
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Publication number: 20240006113Abstract: An inductor includes a coil, a conductive lead frame, and a housing. The coil includes a coil body and a lead protruding from the coil body. The lead has a U-bend portion. The lead is electrically fixed onto the conductive lead frame. The housing encapsulates the coil and exposes the conductive lead frame. A method of manufacturing an inductor includes the following steps: providing a coil, providing a conductive lead frame, making a lead of the coil be electrically fixed onto the conductive lead frame, bending the lead to form a U-bend portion and make the main body of the coil close to a portion of the lead that connects with the conductive lead frame, and forming a housing to encapsulate the coil and expose the conductive lead frame.Type: ApplicationFiled: June 4, 2023Publication date: January 4, 2024Applicant: DARFON ELECTRONICS CORP.Inventors: Zuei-Chown Jou, Chih-Ho Liu, Jui-Wen Kuo, Chi-Ming Huang, Bo-Yu Huang, Yao-Tsung Chen
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Patent number: 11842481Abstract: A method includes: receiving a defect map from a defect scanner, wherein the defect map comprises at least one defect location of a semiconductor workpiece; annotating the defect map with a reference fiducial location of the semiconductor workpiece; determining a detected fiducial location within image data of the semiconductor workpiece; determining an offset correction based on comparing the detected fiducial location with the reference fiducial location; producing a corrected defect map by applying the offset correction to the defect map, wherein the applying the offset correction translocates the at least one defect location; and transferring the corrected defect map to a defect reviewer configured to perform root cause analysis based on the corrected defect map.Type: GrantFiled: August 4, 2022Date of Patent: December 12, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chien-Ko Liao, Ya-Hsun Hsueh, Sheng-Hsiang Chuang, Hsu-Shui Liu, Jiun-Rong Pai, Shou-Wen Kuo
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Publication number: 20230395320Abstract: An integrated-type coupled inductor is applied to a related manufacturing method and includes a lead frame, a first coil, a second coil and a magnetic packing component. The lead frame has a first surface and a second surface opposite to each other and includes four pins. The first coil is disposed on the first surface and coupled to two of the four pins. The second coil is disposed on the second surface and coupled to other pins. The magnetic packing component covers the first coil and the second coil to expose parts of the four pins.Type: ApplicationFiled: May 29, 2023Publication date: December 7, 2023Applicant: DARFON ELECTRONICS CORP.Inventors: Chih-Ho Liu, Jui-Wen Kuo, Chi-Ming Huang, Bo-Yu Huang, Yao-Tsung Chen
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Publication number: 20230386887Abstract: A system and method for cleaning ring frames is disclosed. In one embodiment, a ring frame processing system includes: a plurality of blades for mechanically removing tapes and tape residues from surfaces of a ring frame; a plurality of wheel brushes for conditioning the surfaces of the ring frame; and a transport mechanism for transporting the ring frame.Type: ApplicationFiled: August 8, 2023Publication date: November 30, 2023Inventors: Chien-Fa Lee, Hsu-Shui Liu, Jiun-Rong Pai, Shou-Wen Kuo, Jian-Hung Cheng, M.C. Lin, C.C. Chien, Hsuan Lee, Boris Huang
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Publication number: 20230376392Abstract: Failover methods and systems for a networked storage environment are provided. In one aspect, a read request associated with a first storage object is received, during a replay of entries of a log stored in a non-volatile memory of a second storage node for a failover operation initiated in response to a failure at a first storage node. The second storage node operates as a partner node of the first storage node. The read request is processed using a filtering data structure that is generated from the log prior to the replay and identifies each log entry. The read request is processed when the log does not have an entry associated with the read request, and when the filtering data structure includes an entry associated with the read request, the requested data is located at the non-volatile memory.Type: ApplicationFiled: August 1, 2023Publication date: November 23, 2023Inventors: Asif Imtiyaz Pathan, Parag Sarfare, Ananthan Subramanian, Szu-Wen Kuo, Santhosh Selvaraj, Nikhil Mattankot
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Publication number: 20230369325Abstract: In an embodiment, a method includes: depositing a protective layer on a source/drain region and a gate mask, the gate mask disposed on a gate structure, the gate structure disposed on a channel region of a substrate, the channel region adjoining the source/drain region; etching an opening through the protective layer, the opening exposing the source/drain region; depositing a metal in the opening and on the protective layer; annealing the metal to form a metal-semiconductor alloy region on the source/drain region; and removing residue of the metal from the opening with a cleaning process, the protective layer covering the gate mask during the cleaning process.Type: ApplicationFiled: July 26, 2023Publication date: November 16, 2023Inventors: Yang-Cheng Wu, Yun-Hua Chen, Wen-Kuo Hsieh, Huan-Just Lin
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Publication number: 20230350610Abstract: Techniques are provided for implementing a garbage collection process and a prediction read ahead mechanism to prefetch keys into memory to improve the efficiency and speed of the garbage collection process. A log structured merge tree is used to store keys of key-value pairs within a key-value store. If a key is no longer referenced by any worker nodes of a distributed storage architecture, then the key can be freed to store other data. Accordingly, garbage collection is performed to identify and free unused keys. The speed and efficiency of garbage collection is improved by dynamically adjusting the amount and rate at which keys are prefetched from disk and cached into faster memory for processing by the garbage collection process.Type: ApplicationFiled: April 28, 2022Publication date: November 2, 2023Inventors: Anil Paul Thoppil, We Sun, Meera Odugoudar, Szu-Wen Kuo, Santhosh Selvaraj