Abstract: A device includes arrays of Non-Volatile Memory (NVM) cells. Reference sequences representing portions of a genome are stored in respective groups of NVM cells. Exact matching phase substring sequences representing portions of at least one sample read are loaded into groups of NVM cells. One or more groups of NVM cells are identified where the stored reference sequence matches the loaded exact matching phase substring sequence using the arrays at Content Addressable Memories (CAMs). Approximate matching phase substring sequences are loaded into groups of NVM cells. One or more groups of NVM cells are identified where the stored reference sequence approximately matches the loaded approximate matching phase substring sequence using the arrays as Ternary CAMs (TCAMs). At least one of the reference sequence and the approximate matching phase substring sequence for each group of NVM cells includes at least one wildcard value when the arrays are used as TCAMs.

Abstract: A non-volatile memory device is configured for in-memory computation of layers of a neural network by storing weight values as conductance values in memory cells formed of a series combination of a threshold switching selector, such as an ovonic threshold switch, and a programmable resistive element, such as a ReRAM element. By scaling the input voltages (representing inputs for the layer of the neural network) relative to the threshold values of the threshold switching selectors, dropout for inputs can be implemented to reduce overfitting by the neural network.

Abstract: An information handling system may include a processor, one or more audio speakers configured to play back audible audio signals, and a basic input/output system (BIOS) comprising a program of instructions comprising boot firmware configured to be the first code executed by the processor when the information handling system is booted or powered on in order to initialize the information handling system for operation. The BIOS may be further configured to monitor for an error occurring during execution of the BIOS and responsive to an error occurring during execution of the BIOS, cause the one or more audio speakers to play back a sequence of one or more multi-frequency audio signals encoding an identity of the error.

Abstract: An all-solid-state battery includes a positive electrode layer including a positive electrode active material layer and a positive electrode current collector; a negative electrode layer including a negative electrode active material layer and a negative electrode current collector; a solid electrolyte layer; and an insulating film, in which the insulating film has therein a through-hole in which a laminate in which the positive electrode active material layer, the solid electrolyte layer, and the negative electrode active material layer are sequentially stacked is housed, the laminate and the insulating film are arranged between the positive electrode current collector and the negative electrode current collector, and an external shape of the insulating film is larger than external shapes of the positive electrode current collector and the negative electrode current collector when viewed in a plan view in a laminating direction of the laminate.

Abstract: Provided is a battery including a battery element having a positive electrode, a negative electrode, and a solid electrolyte layer between the positive electrode and the negative electrode, and further including an exterior body covering the battery element, in which at least one of the positive electrode, the negative electrode, and the solid electrolyte layer includes a solid electrolyte represented by Formula (1) of Li3+aE1-bGbDcXd-e, and a moisture content in a housing space between the battery element and the exterior body is less than 1100 ppmv.

Abstract: An innovative low-bit-width device may include a first digital-to-analog converter (DAC), a second DAC, a plurality of non-volatile memory (NVM) weight arrays, one or more analog-to-digital converters (ADCs), and a neural circuit. The first DAC is configured to convert a digital input signal into an analog input signal. The second DAC is configured to convert a digital previous hidden state (PHS) signal into an analog PHS signal. NVM weight arrays are configured to compute vector matrix multiplication (VMM) arrays based on the analog input signal and the analog PHS signal. The NVM weight arrays are coupled to the first DAC and the second DAC. The one or more ADCs are coupled to the plurality of NVM weight arrays and are configured to convert the VMM arrays into digital VMM values. The neural circuit is configured to process the digital VMM values into a new hidden state.

Abstract: A safety socket module includes: a shell; an upper cover, configured to cover the shell, where jacks are provided on the upper cover; compartments, where the number of the compartments corresponds to the number of the jacks, each of the compartments is arranged in the shell and below a respective jack of the jacks, and an interior of each of the compartments is accessible from an exterior of the shell through the respective jack; waterproof electrical connection switches, arranged in the compartments and configured to asynchronously control connection and disconnection of a circuit between a power supply and a plug of an electric appliance; and lock control members, respectively arranged in the compartments and aligned with the jacks; where each of the waterproof electrical connection switches includes a waterproof capsule, and a movable contact piece and a static contact piece arranged opposite to each other in the waterproof capsule.

Abstract: A safety socket module includes: a shell; an upper cover, configured to cover the shell, where jacks are provided on the upper cover; compartments, where the number of the compartments corresponds to the number of the jacks, each of the compartments is arranged in the shell and below a respective jack of the jacks, and an interior of each of the compartments is accessible from an exterior of the shell through the respective jack; waterproof electrical connection switches, arranged in the compartments and configured to asynchronously control connection and disconnection of a circuit between a power supply and a plug of an electric appliance; and lock control members, respectively arranged in the compartments and aligned with the jacks; where each of the waterproof electrical connection switches includes a waterproof capsule, and a movable contact piece and a static contact piece arranged opposite to each other in the waterproof capsule.

Abstract: A non-volatile memory device is configured for in-memory computation of discrete Fourier transformations and their inverses. The real and imaginary components of the twiddle factors are stored as conductance values of memory cells in non-volatile memory arrays having a cross-point structure. The real and imaginary components of inputs are encoded as word line voltages applied to the arrays. Positive and negative valued components of the twiddle factors are stored separately and positive and negative of the inputs are separately applied to the arrays. Real and imaginary parts of the outputs for the discrete Fourier transformation are determined from combinations of the output currents from the arrays.

Abstract: A non-volatile memory device includes arrays of non-volatile memory cells that are configured to the store weights for a recurrent neural network (RNN) inference engine with a gated recurrent unit (GRU) cell. A set three non-volatile memory arrays, such as formed of storage class memory, store a corresponding three sets of weights and are used to perform compute-in-memory inferencing. The hidden state of a previous iteration and an external input are applied to the weights of the first and the of second of the arrays, with the output of the first array used to generate an input to the third array, which also receives the external input. The hidden state of the current generation is generated from the outputs of the second and third arrays.

Abstract: Technology for reconfigurable input precision in-memory computing is disclosed herein. Reconfigurable input precision allows the bit resolution of input data to be changed to meet the requirements of in-memory computing operations. Voltage sources (that may include DACs) provide voltages that represent input data to memory cell nodes. The resolution of the voltage sources may be reconfigured to change the precision of the input data. In one parallel mode, the number of DACs in a DAC node is used to configure the resolution. In one serial mode, the number of cycles over which a DAC provides voltages is used to configure the resolution. The memory system may include relatively low resolution voltage sources, which avoids the need to have complex high resolution voltage sources (e.g., high resolution DACs). Lower resolution voltage sources can take up less area and/or use less power than higher resolution voltage sources.

Abstract: Systems and methods for reducing the impact of defects within a crossbar memory array when performing multiplication operations in which multiple control lines are concurrently selected are described. A group of memory cells within the crossbar memory array may be controlled by a local word line that is controlled by a local word line gating unit that may be configured to prevent the local word line from being biased to a selected word line voltage during an operation; the local word line may instead be set to a disabling voltage during the operation such that the memory cell currents through the group of memory cells are eliminated. If a defect has caused a short within one of the memory cells of the group of memory cells, then the local word line gating unit may be programmed to hold the local word line at the disabling voltage during multiplication operations.

Abstract: A non-volatile memory device is configured for in-memory computation of layers of a neural network by storing weight values as conductance values in memory cells formed of a series combination of a threshold switching selector, such as an ovonic threshold switch, and a programmable resistive element, such as a ReRAM element. By scaling the input voltages (representing inputs for the layer of the neural network) relative to the threshold values of the threshold switching selectors, dropout for inputs can be implemented to reduce overfitting by the neural network.

Abstract: Enhanced techniques and circuitry are presented herein for artificial neural networks. These artificial neural networks are formed from artificial synapses, which in the implementations herein comprise a memory arrays having non-volatile memory elements. In one implementation, an apparatus comprises a plurality of non-volatile memory arrays configured to store weight values for an artificial neural network. Each of the plurality of non-volatile memory arrays can be configured to receive data from a unified buffer shared among the plurality of non-volatile memory arrays, operate on the data, and shift at least portions of the data to another of the plurality of non-volatile memory arrays.

Abstract: To improve efficiencies for inferencing operations of neural networks, ensemble neural networks are used for compute-in-memory inferencing. In an ensemble neural network, the layers of a neural network are replaced by an ensemble of multiple smaller neural network generated from subsets of the same training data as would be used for the layers of the full neural network. Although the individual smaller network layers are “weak classifiers” that will be less accurate than the full neural network, by combining their outputs, such as in majority voting or averaging, the ensembles can have accuracies approaching that of the full neural network. Ensemble neural networks for compute-in-memory operations can have their efficiency further improved by implementations based binary memory cells, such as by binary neural networks using binary valued MRAM memory cells. The size of an ensemble can be increased or decreased to optimize the system according to error requirements.

Abstract: A coffee or tea brewing apparatus comprising a hollow cylinder with top and bottom openings, a permeable filter, a filter retaining ring which attaches to the bottom end of the hollow cylinder and encloses the bottom opening of the hollow cylinder with the permeable filter, a support ring to support the hollow cylinder above an open vessel, and a flexible lid. Coffee grounds or tea leaves are mixed with water inside the hollow cylinder which will then drain through the removable filter effectively separating any liquids into an open vessel while retaining undissolved solids within the hollow cylinder. The flexible lid may be used to enclose the top of the hollow cylinder and pressed on to produce a positive air pressure within the filter assembly to force the liquid through the permeable filter when a faster flow rate is desired.

Abstract: The present invention relates to organic polymer synthetic materials, and discloses a self-curing organic synthetic resin composition for additive manufacturing. The self-curing organic synthetic resin composition includes 30-75% by weight of a linear thermoplastic phenolic resin and 25-70% by weight of a phenol modified furan resin. The self-curing organic synthetic resin composition is prepared through three stages. The linear thermoplastic phenolic resin prepared in stage (1) and the phenol modified furan resin prepared in stage (2) are mixed in a certain weight ratio in stage (3) to obtain the self-curing organic synthetic resin composition for additive manufacturing, which has the advantages of high strength at normal temperature, excellent resistance to high temperature, high activity and excellent collapsibility. Thus, the self-curing organic synthetic resin composition provided in the invention is suitable for additive manufacturing, and particularly for 3D printing in mold casting.

Abstract: Non-volatile memory structures are presented for a content addressable memory (CAM) that can perform in-memory search operations for both ternary and binary valued key values. Each ternary or binary valued key bit is stored in a pair of memory cells along a bit line of a NAND memory array, with the stored keys searched by applying each ternary or binary valued bit of an input key as voltage levels on a pair of word lines. The system is highly scalable. The system can also be used to perform nearest neighbor searches between stored vectors and an input vector to find stored vectors withing a specified Hamming distance of the input vector.

Abstract: Exemplary methods and apparatus are disclosed that implement super-sparse image/video compression by storing image dictionary elements within a cross-bar resistive random access memory (ReRAM) array (or other suitable cross-bar NVM array). In illustrative examples, each column of the cross-bar ReRAM array stores the values for one dictionary element (such as one 4×4 dictionary element). Methods and apparatus are described for training (configuring) the cross-bar ReRAM array to generate and store the dictionary elements by sequentially applying patches from training images to the array using an unstructured Hebbian training procedure. Additionally, methods and apparatus are described for compressing an input image by applying patches from the input image to the ReRAM array to read out cross-bar column indices identifying the columns storing the various dictionary elements that best fit the image. This may be done in parallel using a set of ReRAM arrays.