Abstract: Enhanced techniques and circuitry are presented herein for artificial neural networks. These artificial neural networks are formed from artificial synapses, which in the implementations herein comprise a memory arrays having non-volatile memory elements. In one implementation, an apparatus comprises a plurality of non-volatile memory arrays configured to store weight values for an artificial neural network. Each of the plurality of non-volatile memory arrays can be configured to receive data from a unified buffer shared among the plurality of non-volatile memory arrays, operate on the data, and shift at least portions of the data to another of the plurality of non-volatile memory arrays.

Abstract: Use of a non-volatile memory array architecture to realize a neural network (BNN) allows for matrix multiplication and accumulation to be performed within the memory array. A unit synapse for storing a weight of a neural network is formed by a differential memory cell of two individual memory cells, such as a memory cells having a programmable resistance, each connected between a corresponding one of a word line pair and a shared bit line. An input is applied as a pattern of voltage values on word line pairs connected to the unit synapses to perform the multiplication of the input with the weight by determining a voltage level on the shared bit line. The results of such multiplications are determined by a sense amplifier, with the results accumulated by a summation circuit. The approach can be extended from binary weights to multi-bit weight values by use of multiple differential memory cells for a weight.

Abstract: Use of a non-volatile memory array architecture to realize a neural network (BNN) allows for matrix multiplication and accumulation to be performed within the memory array. A unit synapse for storing a weight of a neural network is formed by a differential memory cell of two individual memory cells, such as a memory cells having a programmable resistance, each connected between a corresponding one of a word line pair and a shared bit line. An input is applied as a pattern of voltage values on word line pairs connected to the unit synapses to perform the multiplication of the input with the weight by determining a voltage level on the shared bit line. The results of such multiplications are determined by a sense amplifier, with the results accumulated by a summation circuit.

Abstract: Use of a NAND array architecture to realize a binary neural network (BNN) allows for matrix multiplication and accumulation to be performed within the memory array. A unit synapse for storing a weight of a BNN is stored in a pair of series connected memory cells. A binary input is applied as a pattern of voltage values on a pair of word lines connected to the unit synapse to perform the multiplication of the input with the weight by determining whether or not the unit synapse conducts. The results of such multiplications are determined by a sense amplifier, with the results accumulated by a counter.

Abstract: A nucleic acid isothermal amplification method is based on a polymerase spiral reaction using only one pair of primers. The method employs a self-spiraling amplification method, and has a high amplification efficiency.

Abstract: Enhanced techniques and circuitry are presented herein for artificial neural networks. These artificial neural networks are formed from artificial neurons, which in the implementations herein comprise a memory array having non-volatile memory elements. Neural connections among the artificial neurons are formed by interconnect circuitry coupled to input control lines and output control lines of the memory array to subdivide the memory array into a plurality of layers of the artificial neural network. Control circuitry is configured to transmit a plurality of iterations of an input value on input control lines of a first layer of the artificial neural network for inference operations by at least one or more additional layers. The control circuitry is also configured to apply an averaging function across output values successively presented on output control lines of a last layer of the artificial neural network from each iteration of the input value.

Abstract: Systems, methods, and computer-readable media are provided for wireless communications and computer networking, including wireless sensor networks. In embodiments, a first device stores an indication of a received second heartbeat signal broadcasted by a second device. The second heartbeat signal is for accessing or maintaining a service provided by a service provider and/or an access network node (AN). The first device generates a first heartbeat signal to include the indication of the second heartbeat signal. The indication of the second heartbeat signal in the first heartbeat signal is for facilitating discovery of the second device by the AN. Other embodiments are disclosed and/or claimed.

Abstract: A cryptographic device and a secret key protection method are provided. The cryptographic device protects a secret key of the cryptographic device when processing a message. The cryptographic device includes: a secret key protection circuit, configured to generate an anti-crack protection signal according to the message and the secret key by a hash calculation circuit; and a cryptographic processor, configured to process the message and the secret key according to the anti-crack protection signal to generate an encrypted message.

Abstract: A nucleic acid isothermal amplification method is based on a polymerase spiral reaction using only one pair of primers. The method employs a self-spiraling amplification method, and has a high amplification efficiency.

Abstract: A control method for a decision feedback equalizer (DFE) includes: generating a channel impulse response (CIR) estimation vector according to an input signal at a CIR estimation frequency; generating an FFE coefficient according to the CIR estimation vector at a first frequency; generating an FBE coefficient according to the CIR estimation vector, and the FFE coefficient at a second frequency; generating a feed-forward equalization filtered result according to the input signal and the FFE coefficient; generating a feed-backward equalization filtered result according to a decision signal and the FBE coefficient; and generating an updated decision signal according to the feed-forward equalization filtered result and the feed-backward equalization filtered result. At least one of the first frequency and the second frequency is smaller than the CIR estimation frequency.

Abstract: A control method for a decision feedback equalizer (DFE) includes: generating a channel impulse response (CIR) estimation vector according to an input signal at a CIR estimation frequency; generating an FFE coefficient according to the CIR estimation vector at a first frequency; generating an FBE coefficient according to the CIR estimation vector, and the FFE coefficient at a second frequency; generating a feed-forward equalization filtered result according to the input signal and the FFE coefficient; generating a feed-backward equalization filtered result according to a decision signal and the FBE coefficient; and generating an updated decision signal according to the feed-forward equalization filtered result and the feed-backward equalization filtered result. At least one of the first frequency and the second frequency is smaller than the CIR estimation frequency.

Abstract: A method for calculating a feed forward equalizer coefficient of a feed forward equalizer in a minimum mean square error decision feedback equalizer (MMSE-DFE) based on a fast transversal recursive least squares (FT-RLS) algorithm is provided. The length of the feed-forward equalizer is LF, which is a positive integer. The method includes an outer iteration having an LF number of iterations. The outer iteration includes an inner iteration having an n number of iterations, where n is an integer between 0 and (LF?2).

Abstract: A cryptographic device and a secret key protection method are provided. The cryptographic device protects a secret key of the cryptographic device when processing a message. The cryptographic device includes: a secret key protection circuit, configured to generate an indecipherable signal according to the message and the secret key by a hash calculation circuit; and a cryptographic processor, configured to process the message and the secret key according to the indecipherable signal to generate an encrypted message.

Abstract: Substrates for solar cells are prepared by etching a plurality of metallurgical grade wafers; depositing aluminum layer on backside of each wafer; depositing a layer of hydrogenated silicon nitride on front surface of each wafer; annealing the wafers at elevated temperature; removing the hydrogenated silicon nitride without disturbing the aluminum layer. A solar cell is then fabricated on the front surface of the wafer while the aluminum remain to serve as the back contact of the cell.

Abstract: A circuit for generating a tracking error signal is provided. The circuit includes a digitizing circuit, a short signal removing circuit and phase comparator. The digitizing circuit receives first and second pick-up signals outputted from a pick-up head, and respectively compares the first and the second pick-up signals with a reference signal to obtain a first digital signal and a second digital signal. The short signal removing circuit is used for removing pulses in the first and the second digital signals, wherein the pulse width of the removed pulses are shorter than a preset time, and the first and second digital without the removed pulses are respectively served as a first determining signal and a second determining signal. The phase comparator receives the first determining signal and the second determining signal for outputting the tracking error signal according to a phase difference between the first and the second determining signals.

Abstract: A circuit for generating a tracking error signal is provided. The circuit includes a digitizing circuit, a short signal removing circuit and phase comparator. The digitizing circuit receives first and second pick-up signals outputted from a pick-up head, and respectively compares the first and the second pick-up signals with a reference signal to obtain a first digital signal and a second digital signal. The short signal removing circuit is used for removing pulses in the first and the second digital signals, wherein the pulse width of the removed pulses are shorter than a preset time, and the first and second digital without the removed pulses are respectively served as a first determining signal and a second determining signal. The phase comparator receives the first determining signal and the second determining signal for outputting the tracking error signal according to a phase difference between the first and the second determining signals.

Abstract: A circuit for generating a tracking error signal is provided. The circuit includes a digitized circuit, a short signal removing circuit and phase comparator. The digitized circuit receives first and second pick-up signals outputted from a pick-up head, and respectively compares the first and the second pick-up signals with a reference signal to obtain a first digital signal and a second digital signal. The short signal removing circuit is used for removing pulses in the first and the second digital signals, wherein the pulse width of the removed pulses are shorter than a preset time, and the first and second digital without the removed pulses are respectively served as a first determining signal and a second determining signal. The phase comparator receives the first determining signal and the second determining signal for outputting the tracking error signal according to a phase difference between the first and the second determining signals.

Abstract: An automatic gain control system with hysteresis switching includes an error calculator for calculating the difference between a first estimation signal and a take over point (TOP) value to produce an error signal. A hysteresis comparator compares the first estimation signal and the TOP value to produce a control signal. A first gain control loop generates a first gain control signal based on the control signal to control a gain of a first variable gain amplifier. A second gain control loop generates a second gain control signal based on the control signal to control a gain of a second variable gain amplifier. As the first estimation signal leaves a hysteresis region of the hysteresis comparator, the first gain control signal is monotonically decreasing and the first gain control signal is monotonically increasing. As a result, the total gain is stable.

Abstract: A control system determines read performance of an optical storage device according to lock performance of a re-timing signal. The control system includes a filtering and re-timing unit for receiving a radio frequency (RF) signal and outputting the re-timing signal and an un-corrected output signal, an error correction unit for receiving the un-corrected output signal and correcting an error bit according to a Reed-Solomon algorithm to generate a corrected output signal, a lock performance detector for receiving the re-timing signal and detecting the lock performance of the re-timing signal and then outputting a lock performance index, and a servo control loop for receiving the RF signal and the lock performance index and thus generating a servo control signal. When the lock performance index does not reach a threshold value, the servo control loop loads other control parameters to improve the read performance of the optical storage device.

Abstract: An automatic gain control system with hysteresis switching includes an error calculator for calculating the difference between a first estimation signal and a take over point (TOP) value to produce an error signal. A hysteresis comparator compares the first estimation signal and the TOP value to produce a control signal. A first gain control loop generates a first gain control signal based on the control signal to control a gain of a first variable gain amplifier. A second gain control loop generates a second gain control signal based on the control signal to control a gain of a second variable gain amplifier. As the first estimation signal leaves a hysteresis region of the hysteresis comparator, the first gain control signal is monotonically decreasing and the first gain control signal is monotonically increasing. As a result, the total gain is stable.