Patents by Inventor Wen Ma
Wen Ma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20100317146Abstract: Substrates for solar cells are prepared by etching a plurality of metallurgical grade wafers; depositing aluminum layer on backside of each wafer; depositing a layer of hydrogenated silicon nitride on front surface of each wafer; annealing the wafers at elevated temperature; removing the hydrogenated silicon nitride without disturbing the aluminum layer. A solar cell is then fabricated on the front surface of the wafer while the aluminum remain to serve as the back contact of the cell.Type: ApplicationFiled: August 24, 2010Publication date: December 16, 2010Applicant: SUNPREME, LTD.Inventors: Ashok Sinha, Wen Ma
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Patent number: 7805662Abstract: An ECC decoder for correcting a coded signal received, which includes a syndrome calculation and errata evaluation device to receive a code word of the coded signal for performing a syndrome calculation to thereby output a syndrome polynomial, and to receive an erasure and errata evaluator polynomial and an errata position for performing an errata evaluation to thereby output an errata and erasure value and correct the coded signal; a key equation solving device to receive the syndrome for generating an erasure and errata locator polynomial and the erasure and errata evaluator polynomial; and an errata position search device to receive the erasure and errata locator polynomial for searching and outputting the errata position. Evaluating the errata and erasure value and calculating the syndrome are performed in pipeline, thereby sharing the hardware and relatively reducing the hardware cost.Type: GrantFiled: February 9, 2007Date of Patent: September 28, 2010Assignee: Sunplus Technology Co., Ltd.Inventors: Ching-Wen Ma, Kuo-Ming Wang, Jia-Ping Chen
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Publication number: 20090206056Abstract: A multi-station workpiece processing system provides a targeted equal share of a regulated input process gas flow to each active processing station of a plurality of active processing stations using a single gas flow regulator for each gas and irrespective of the number of inactive processing stations.Type: ApplicationFiled: February 6, 2009Publication date: August 20, 2009Inventors: Songlin Xu, Daniel J. Devine, Wen Ma, Ce Qin, Vijay Vaniapura
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Publication number: 20090069926Abstract: CNC apparatus having a mechanism for controlling length variation of a lead screw due to thermal expansion and method therefore when the apparatus is rotating in high speed and/or when load is high are disclosed. The lead screw is supported by two spaced ball bearing sets and is hollow to permit cooling fluid to flow through. A deflection detecting unit is disposed proximate one ball bearing set for detecting its deflection. In one embodiment, an adjusting nut is operatively connected to one end of the lead screw and is adapted to pre-stress the ball bearing set. The method includes pre-stressing the ball bearing set for deflecting in one direction and in operation in response to detecting the ball bearing set deflected in an opposite direction cooling the lead screw for substantially maintaining its length unchanged with respect to a bed.Type: ApplicationFiled: September 11, 2007Publication date: March 12, 2009Inventor: Tsu-Wen Ma
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Publication number: 20080310273Abstract: A circuit for generating a tracking error signal is provided. The circuit includes a digitized circuit, a short signal removing circuit and phase comparator. The digitized circuit receives first and second pick-up signals outputted from a pick-up head, and respectively compares the first and the second pick-up signals with a reference signal to obtain a first digital signal and a second digital signal. The short signal removing circuit is used for removing pulses in the first and the second digital signals, wherein the pulse width of the removed pulses are shorter than a preset time, and the first and second digital without the removed pulses are respectively served as a first determining signal and a second determining signal. The phase comparator receives the first determining signal and the second determining signal for outputting the tracking error signal according to a phase difference between the first and the second determining signals.Type: ApplicationFiled: June 13, 2008Publication date: December 18, 2008Inventors: Ching-Wen MA, Yung-Chi YANG
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Publication number: 20080115018Abstract: A control system determines read performance of an optical storage device according to lock performance of a re-timing signal. The control system includes a filtering and re-timing unit for receiving a radio frequency (RF) signal and outputting the re-timing signal and an un-corrected output signal, an error correction unit for receiving the un-corrected output signal and correcting an error bit according to a Reed-Solomon algorithm to generate a corrected output signal, a lock performance detector for receiving the re-timing signal and detecting the lock performance of the re-timing signal and then outputting a lock performance index, and a servo control loop for receiving the RF signal and the lock performance index and thus generating a servo control signal. When the lock performance index does not reach a threshold value, the servo control loop loads other control parameters to improve the read performance of the optical storage device.Type: ApplicationFiled: November 9, 2007Publication date: May 15, 2008Inventors: Ching-Wen Ma, Zheng-Xiong Chen, Shih-Hsien Liu
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Publication number: 20070204207Abstract: An ECC decoder for correcting a coded signal received, which includes a syndrome calculation and errata evaluation device to receive a code word of the coded signal for performing a syndrome calculation to thereby output a syndrome polynomial, and to receive an erasure and errata evaluator polynomial and an errata position for performing an errata evaluation to thereby output an errata and erasure value and correct the coded signal; a key equation solving device to receive the syndrome for generating an erasure and errata locator polynomial and the erasure and errata evaluator polynomial; and an errata position search device to receive the erasure and errata locator polynomial for searching and outputting the errata position. Evaluating the errata and erasure value and calculating the syndrome are performed in pipeline, thereby sharing the hardware and relatively reducing the hardware cost.Type: ApplicationFiled: February 9, 2007Publication date: August 30, 2007Applicant: Sunplus Technology Co., Ltd.Inventors: Ching-Wen Ma, Kuo-Ming Wang, Jia-Ping Chen
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Patent number: 7187739Abstract: A timing recovery circuit and related method is disclosed. The timing recovery circuit encompasses a converter, an interpolator, a phase error detector, an adjustment circuit, and a calculation circuit. The converter samples an input signal to generate an intermediate signal carrying samples of the input signal, while the interpolator inserts an interpolating sample into the intermediate signal in response to a control value to generate an output signal. The phase error detector outputs a phase error of the output signal. The adjustment circuit updates an over-sampling ratio according to a pair of first and second thresholds, and a counting value adjusted in response to the phase error and a median reference value. Finally, the calculation circuit derives the control value from the updated over-sampling ratio, and transferring the control value to the interpolator.Type: GrantFiled: May 16, 2003Date of Patent: March 6, 2007Assignee: Via Technologies, Inc.Inventor: Ching-Wen Ma
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Publication number: 20070047448Abstract: A network equipment testing method and system is proposed, which is designed for use with a network system based on a server-client architecture for implementing a data transmission reliability testing procedure concurrently on one or more pieces of network equipment, and which is characterized by the utilization of a universally acceptable and recognized network testing standard for performing a data transmission reliability testing procedure.Type: ApplicationFiled: August 24, 2005Publication date: March 1, 2007Inventors: Shih-Hua Chiu, Chun-Wen Ma, Yung-Yuan Wu
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Publication number: 20070009074Abstract: A timing recovery apparatus and method with frequency protection are provided. The apparatus uses a frequency estimator to calculate and store an estimated frequency value as a pre-stored estimated frequency value when timing quality is good. A defect detector is used to determine whether a defective portion on a disk medium has been detected. When a defective portion has been detected, the pre-stored estimated frequency value is then used as the basis of phase lock and frequency lock to generate a reference clock. As the read operation performed over the defective portion is finished, the normal frequency lock mechanism is restarted. At this moment, the frequency lock mechanism can take less time to lock the input signal. Thus, the invention significantly reduces the missing readable data due to loss of frequency lock, and never breaks the normal tracking-frequency operation of the frequency lock mechanism.Type: ApplicationFiled: July 7, 2006Publication date: January 11, 2007Inventor: Ching-Wen Ma
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Patent number: 6801514Abstract: A communications system providing SDMA communication channels in a non-SDMA (non-spatial division multiple access) system and used in a specific area to establish wireless communications with mobile stations in the area comprises a smart antenna to establish wireless communications with the mobile stations, a base station controller managing transmissions and receiving information between every mobile station and an outgoing communications network, a plurality of base transceiver stations electrically connected with the base station controller, each of them establishing the wireless communications between the mobile stations and the base station controller, and a spatial spectrum management system connected between the smart antenna and the base transceiver stations.Type: GrantFiled: February 6, 2001Date of Patent: October 5, 2004Assignee: BenQ CorporationInventor: Ching-Wen Ma
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Publication number: 20030215036Abstract: A timing recovery circuit and related method is disclosed. The timing recovery circuit encompasses a converter, an interpolator, a phase error detector, an adjustment circuit, and a calculation circuit. The converter samples an input signal to generate an intermediate signal carrying samples of the input signal, while the interpolator inserts an interpolating sample into the intermediate signal in response to a control value to generate an output signal. The phase error detector outputs a phase error of the output signal. The adjustment circuit updates an over-sampling ratio according to a pair of first and second thresholds, and a counting value adjusted in response to the phase error and a median reference value. Finally, the calculation circuit derives the control value from the updated over-sampling ratio, and transferring the control value to the interpolator.Type: ApplicationFiled: May 16, 2003Publication date: November 20, 2003Inventor: Ching-Wen Ma
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Publication number: 20030047299Abstract: An investment molding flask assembly having a base with a central positioning boss protruded from a center thereof and at least one positioning annular groove defined therein around the central positioning boss, and a conical sleeve formed with a small opening end to be securely positioned on the base without any displacement in horizontal directions by means of the central positioning boss or the positioning annular groove. Whereby, the conical sleeve can be readily removable from a solidified semi-finished investment mold, and then the solidified semi-finished investment mold is sent into an oven independently for heating. Therefore the sleeve can be used repeatedly, and the investment mold can be manufactured rapidly and readily.Type: ApplicationFiled: September 12, 2001Publication date: March 13, 2003Inventor: Ching-Wen Ma
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Patent number: 6468927Abstract: Gap-fill and damascene methods are disclosed for depositing an insulating thin film of nitrofluorinated silicate glass on a substrate in a process chamber. A high-density plasma, generated from a gaseous mixture of silicon-, fluorine-, oxygen-, and nitrogen-containing gases, deposits a layer of nitrofluorinated silicate glass onto the substrate. For gap-fill applications, the substrate is biased with a bias power density between 4.8 and 11.2 W/cm2 and the ratio of flow rate for the oxygen-containing gas to the combined flow rate for all silicon-containing gases in the process chamber is between 1.0 and 1.8, preferably between 1.2 and 1.4. For damascene applications, the bias power density is less than 3.2 W/cm2, preferably 1.6 W/cm2, and the flow rate ratio is between 1.2 and 3.0. Using optimized parameters, the thin film has a lower dielectric constant and better adhesion properties than fluorosilicate glass.Type: GrantFiled: May 19, 2000Date of Patent: October 22, 2002Assignee: Applied Materials, Inc.Inventors: Lin Zhang, Wen Ma, Zhuang Li
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Publication number: 20010012278Abstract: A communications system providing SDMA communication channels in a non-SDMA (non-spatial division multiple access) system and used in a specific area to establish wireless communications with mobile stations in the area comprises a smart antenna to establish wireless communications with the mobile stations, a base station controller managing transmissions and receiving information between every mobile station and an outgoing communications network, a plurality of base transceiver stations electrically connected with the base station controller, each of them establishing the wireless communications between the mobile stations and the base station controller, and a spatial spectrum management system connected between the smart antenna and the base transceiver stations.Type: ApplicationFiled: February 6, 2001Publication date: August 9, 2001Inventor: Ching-Wen Ma
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Patent number: 5956473Abstract: The present application discloses methods to provide defect management, wear leveling and data security to a mass storage system implemented using flash memory. The flash memory is organized into a plurality of blocks. Each block has a special region for storing its attributes. In defect management, defects arising from manufacturing and on-the-fly defects are scanned. Defective blocks are marked by altering its attributes. The present application also discloses a wear leveling method in which the difference between the number of erasures of any two blocks (except the defective blocks) is within a predetermined value. The present application further discloses a new error detection and correction method. The same data is stored in two separate memory locations. The content of these two locations are later "ored" or "anded" together (depending on the nature of error giving rise to the error) to recover the correct data.Type: GrantFiled: November 25, 1996Date of Patent: September 21, 1999Assignee: Macronix International Co., Ltd.Inventors: Chung-Wen Ma, Chun-Hung Lin, Tai-Yao Lee, Li-Jen Lee, Ju-Xu Lee, Ting-Chung Hu
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Patent number: 5933368Abstract: An architecture for a mass storage system using flash memory is described. This architecture involves organizing the flash memory into a plurality of blocks. These blocks are then divided into several categories. One of the categories is a working category used to store data organized in accordance with a pre-defined addressing scheme (such as the logical block address used in Microsoft's operating system). The other category is a temporary buffer used to store data intended to be written to one of the working blocks. Another category contains blocks that need to be erased. When data is written into the mass storage system, a block in the second category is allocated from a block in the third category. The allocated block will then be changed to a block in the first category when writing to the allocated block is completed. The correspond block in the first category is placed into the third category. As a result, blocks can be recycled.Type: GrantFiled: April 27, 1998Date of Patent: August 3, 1999Assignee: Macronix International Co., Ltd.Inventors: Chung-Wen Ma, Chu-Hung Lin, Tai-Yao Lee, Li-Jen Lee, Ju-Xu Lee, Ting-Chung Hu
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Patent number: 5745418Abstract: An architecture for a mass storage system using flash memory is described. This architecture involves organizing the flash memory into a plurality of blocks. These blocks are then divided into several categories. One of the categories is a working category used to store data organized in accordance with a pre-defined addressing scheme (such as the logical block address used in Microsoft's operating system). The other category is a temporary buffer used to store data intended to be written to one of the working blocks. Another category contains blocks that need to be erased. When data is written into the mass storage system, a block in the second category is allocated from a block in the third category. The allocated block will then be changed to a block in the first category when writing to the allocated block is completed. The correspond block in the first category is placed into the third category. As a result, blocks can be recycled.Type: GrantFiled: November 25, 1996Date of Patent: April 28, 1998Assignee: Macronix International Co., Ltd.Inventors: Chung-Wen Ma, Chun-Hung Lin, Tai-Yao Lee, Li-Jen Lee, Ju-Xu Lee, Ting-Chung Hu