Abstract: Methods of forming a semiconductor device structure are described. In some embodiments, the method includes forming an interconnect structure over a substrate. The forming the interconnect structure over the semiconductor device structure includes forming a dielectric layer, then performing an annealing process, then forming one or more openings in the dielectric layer, then performing a first ultraviolet (UV) curing process, and then forming conductive features in the one or more openings.

Abstract: In a method of manufacturing a semiconductor device, a fin structure having a channel region protruding from an isolation insulating layer disposed over a semiconductor substrate is formed, a cleaning operation is performed, and an epitaxial semiconductor layer is formed over the channel region. The cleaning operation and the forming the epitaxial semiconductor layer are performed in a same chamber without breaking vacuum.

Abstract: A method includes forming a dielectric layer over a contact pad of a device, forming a first polymer layer over the dielectric layer, forming a first conductive line and a first portion of a second conductive line over the first polymer layer, patterning a photoresist to form an opening over the first portion of the second conductive feature, wherein after patterning the photoresist the first conductive line remains covered by photoresist, forming a second portion of the second conductive line in the opening, wherein the second portion of the second conductive line physically contacts the first portion of the second conductive line, and forming a second polymer layer extending completely over the first conductive line and the second portion of the second conductive line.

Abstract: An electronic device is disclosed. The electronic device includes a substrate, a plurality of color filters disposed on the substrate, an optical film disposed on the plurality of color filter, and a defect disposed between the substrate and the optical film. The optical film has a first base, a protective layer on the first base, and a second base between the first base and the protective layer and having a first processed area. In a top view of the electronic device, the first processed area corresponds to the defect and at least partially overlaps at least two color filters.

Abstract: Methods for fabricating semiconductor structures are provided. An exemplary method includes forming a first transistor structure and a second transistor structure over a substrate, wherein each transistor structure includes at least one nanosheet. The method further includes depositing a metal over each transistor structure and around each nanosheet; depositing a coating over the metal; depositing a mask over the coating; and patterning the mask to define a patterned mask, wherein the patterned mask lies over a masked portion of the coating and the second transistor structure, and wherein the patterned mask does not lie over an unmasked portion of the coating and the first transistor structure. The method further includes etching the unmasked portion of the coating and the metal over the first transistor structure using a dry etching process with a process pressure of from 30 to 60 (mTorr).

Abstract: Provided are structures and methods for forming structures with sloping surfaces of a desired profile. An exemplary method includes performing a first etch process to differentially etch a gate material to a recessed surface, wherein the recessed surface includes a first horn at a first edge, a second horn at a second edge, and a valley located between the first horn and the second horn; depositing an etch-retarding layer over the recessed surface, wherein the etch-retarding layer has a central region over the valley and has edge regions over the horns, and wherein the central region of the etch-retarding layer is thicker than the edge regions of the etch-retarding layer; and performing a second etch process to recess the horns to establish the gate material with a desired profile.

Abstract: Methods of cutting gate structures and fins, and structures formed thereby, are described. In an embodiment, a substrate includes first and second fins and an isolation region. The first and second fins extend longitudinally parallel, with the isolation region disposed therebetween. A gate structure includes a conformal gate dielectric over the first fin and a gate electrode over the conformal gate dielectric. A first insulating fill structure abuts the gate structure and extends vertically from a level of an upper surface of the gate structure to at least a surface of the isolation region. No portion of the conformal gate dielectric extends vertically between the first insulating fill structure and the gate electrode. A second insulating fill structure abuts the first insulating fill structure and an end sidewall of the second fin. The first insulating fill structure is disposed laterally between the gate structure and the second insulating fill structure.

Abstract: Disclosed is a semiconductor fabrication method. The method includes forming a gate stack in an area previously occupied by a dummy gate structure; forming a first metal cap layer over the gate stack; forming a first dielectric cap layer over the first metal cap layer; selectively removing a portion of the gate stack and the first metal cap layer while leaving a sidewall portion of the first metal cap layer that extends along a sidewall of the first dielectric cap layer; forming a second metal cap layer over the gate stack and the first metal cap layer wherein a sidewall portion of the second metal cap layer extends further along a sidewall of the first dielectric cap layer; forming a second dielectric cap layer over the second metal cap layer; and flattening a top layer of the first dielectric cap layer and the second dielectric cap layer using planarization operations.

Abstract: A semiconductor device is disclosed. The semiconductor device includes a semiconductor fin. The semiconductor device includes first spacers over the semiconductor fin. The semiconductor device includes a metal gate structure, over the semiconductor fin, that is sandwiched at least by the first spacers. The semiconductor device includes a gate electrode contacting the metal gate structure. An interface between the metal gate structure and the gate electrode has its side portions extending toward the semiconductor fin with a first distance and a central portion extending toward the semiconductor fin with a second distance, the first distance being substantially less than the second distance.

Abstract: Methods of forming a semiconductor device structure are described. In some embodiments, the method includes forming an interconnect structure over a substrate. The forming the interconnect structure over the semiconductor device structure includes forming a dielectric layer, then performing an annealing process, then forming one or more openings in the dielectric layer, then performing a first ultraviolet (UV) curing process, and then forming conductive features in the one or more openings.

Abstract: Methods of cutting gate structures and fins, and structures formed thereby, are described. In an embodiment, a substrate includes first and second fins and an isolation region. The first and second fins extend longitudinally parallel, with the isolation region disposed therebetween. A gate structure includes a conformal gate dielectric over the first fin and a gate electrode over the conformal gate dielectric. A first insulating fill structure abuts the gate structure and extends vertically from a level of an upper surface of the gate structure to at least a surface of the isolation region. No portion of the conformal gate dielectric extends vertically between the first insulating fill structure and the gate electrode. A second insulating fill structure abuts the first insulating fill structure and an end sidewall of the second fin. The first insulating fill structure is disposed laterally between the gate structure and the second insulating fill structure.

Abstract: The present invention provides a method of dynamic thermal management applied to a portable device, wherein the method includes the steps of: obtaining a surface temperature of the portable device; obtaining a junction temperature of a chip of the portable device; and calculating an upper limit of the junction temperature according to the junction temperature and the surface temperature.

Abstract: The present disclosure provides a probing apparatus for semiconductor devices using pressurized fluid to control the testing conditions. The probing apparatus includes a housing configured to define a testing chamber; a device holder positioned on the housing and configured to hold and support at least one device under test; a platen positioned on the housing and configured to retain at least one probe; a card holder positioned on the platen and configured to hold a probe card including the probe; and at least one flow line positioned in the card holder. The flow line is configured to flow a fluid therein to adjust the temperature of the device under test.

Abstract: A semiconductor package includes a package substrate having a top surface and a bottom surface, and a stiffener ring mounted on the top surface of the package substrate. The stiffener ring includes a reinforcement rib that is coplanar with the stiffener ring on the top surface of the package substrate. At least two compartments are defined by the stiffener ring and the reinforcement rib. At least two individual chip packages are mounted on chip mounting regions within the at least two compartments, respectively, thereby constituting a package array on the package substrate.

Abstract: A method includes depositing a dielectric layer over a substrate, and etching the dielectric layer to form an opening and to expose a first conductive feature underlying the dielectric layer. The dielectric layer is formed using a precursor including nitrogen therein. The method further includes depositing a sacrificial spacer layer extending into the opening, and patterning the sacrificial spacer layer to remove a bottom portion of the sacrificial spacer layer. A vertical portion of the sacrificial spacer layer in the opening and on sidewalls of the dielectric layer is left to form a ring. A second conductive feature is formed in the opening. The second conductive feature is encircled by the ring, and is over and electrically coupled to the first conductive feature. At least a portion of the ring is removed to form an air spacer.

Abstract: Evaluating the performance of an X-ray tube by: recording arcing events that occurred during the use of the X-ray tube; classifying the arcing events by severity; generating, on the basis of the classified arcing events, a first growth pattern for occurrences of arcing events; and determining a level of bubbles in the X-ray tube by finding, on the basis of the first growth pattern, a matching second growth pattern associated with a known level of bubbles in the X-ray tube. An X-ray tube may be checked and replaced in a timely manner, without the need for an on-site inspection, by remotely predicting trends or patterns for growth of levels of bubbles in the X-ray tube.

Abstract: Methods of forming a semiconductor device structure are described. In some embodiments, the method includes forming an interconnect structure over a substrate. The forming the interconnect structure over the semiconductor device structure includes forming a dielectric layer, then performing an annealing process, then forming one or more openings in the dielectric layer, then performing a first ultraviolet (UV) curing process, and then forming conductive features in the one or more openings.

Abstract: Improved gate structures, methods for forming the same, and semiconductor devices including the same are disclosed. In an embodiment, a semiconductor device includes a gate structure over a semiconductor substrate, the gate structure including a high-k dielectric layer; a gate electrode over the high-k dielectric layer; a conductive cap over and in contact with the high-k dielectric layer and the gate electrode, a top surface of the conductive cap being convex; and first gate spacers on opposite sides of the gate structure, the high-k dielectric layer and the conductive cap extending between opposite sidewalls of the first gate spacers.

Abstract: Methods of cutting gate structures and fins, and structures formed thereby, are described. In an embodiment, a substrate includes first and second fins and an isolation region. The first and second fins extend longitudinally parallel, with the isolation region disposed therebetween. A gate structure includes a conformal gate dielectric over the first fin and a gate electrode over the conformal gate dielectric. A first insulating fill structure abuts the gate structure and extends vertically from a level of an upper surface of the gate structure to at least a surface of the isolation region. No portion of the conformal gate dielectric extends vertically between the first insulating fill structure and the gate electrode. A second insulating fill structure abuts the first insulating fill structure and an end sidewall of the second fin. The first insulating fill structure is disposed laterally between the gate structure and the second insulating fill structure.

Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The memory device is arranged in a plurality of logical planes and the controller is configured to write log data and user data to separate planes within the memory device, such that the log data and user data are isolated from each other on separate planes. The controller is configured to read log data from one plane and user data on another plane simultaneously, where the log data and the user data are isolated from each other on separate planes.