Patents by Inventor Wen Pan
Wen Pan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11502076Abstract: Methods of cutting gate structures and fins, and structures formed thereby, are described. In an embodiment, a substrate includes first and second fins and an isolation region. The first and second fins extend longitudinally parallel, with the isolation region disposed therebetween. A gate structure includes a conformal gate dielectric over the first fin and a gate electrode over the conformal gate dielectric. A first insulating fill structure abuts the gate structure and extends vertically from a level of an upper surface of the gate structure to at least a surface of the isolation region. No portion of the conformal gate dielectric extends vertically between the first insulating fill structure and the gate electrode. A second insulating fill structure abuts the first insulating fill structure and an end sidewall of the second fin. The first insulating fill structure is disposed laterally between the gate structure and the second insulating fill structure.Type: GrantFiled: November 30, 2018Date of Patent: November 15, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ryan Chia-Jen Chen, Cheng-Chung Chang, Shao-Hua Hsu, Yu-Hsien Lin, Ming-Ching Chang, Li-Wei Yin, Tzu-Wen Pan, Yi-Chun Chen
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Publication number: 20220359376Abstract: An integrated circuit structure includes a substrate, a transistor, a first dielectric layer, a metal contact, a first low-k dielectric layer, a second dielectric layer, and a first metal feature. The transistor is over the substrate. The first dielectric layer is over the transistor. The metal contact is in the first dielectric layer and electrically connected to the transistor. The first low-k dielectric layer is over the first dielectric layer. The second dielectric layer is over the first low-k dielectric layer and has a dielectric constant higher than a dielectric constant of the first low-k dielectric layer. The first metal feature extends through both second dielectric layer and the first low-k dielectric layer to the metal contact.Type: ApplicationFiled: October 1, 2021Publication date: November 10, 2022Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yi-Wen PAN, Chung-Chi KO
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Publication number: 20220262691Abstract: A semiconductor package includes a package substrate having a top surface and a bottom surface, and a stiffener ring mounted on the top surface of the package substrate. The stiffener ring includes a reinforcement rib that is coplanar with the stiffener ring on the top surface of the package substrate. At least two compartments are defined by the stiffener ring and the reinforcement rib. At least two individual chip packages are mounted on chip mounting regions within the at least two compartments, respectively, thereby constituting a package array on the package substrate.Type: ApplicationFiled: March 2, 2022Publication date: August 18, 2022Applicant: Media Tek Inc.Inventors: Chi-Wen Pan, I-Hsuan Peng, Sheng-Liang Kuo, Yi-Jou Lin, Tai-Yu Chen
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Publication number: 20220221508Abstract: The present disclosure provides a probing apparatus for semiconductor devices using pressurized fluid to control the testing conditions. The probing apparatus includes a housing configured to define a testing chamber; a device holder positioned on the housing and configured to hold and support at least one device under test; a platen positioned on the housing and configured to retain at least one probe; a card holder positioned on the platen and configured to hold a probe card including the probe; and at least one flow line positioned in the card holder. The flow line is configured to flow a fluid therein to adjust the temperature of the device under test.Type: ApplicationFiled: January 11, 2021Publication date: July 14, 2022Inventors: Choon Leong Lou, Chen-Wen Pan, Jung-Chieh Liu
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Patent number: 11302592Abstract: A semiconductor package includes a package substrate having a top surface and a bottom surface, and a stiffener ring mounted on the top surface of the package substrate. The stiffener ring includes a reinforcement rib that is coplanar with the stiffener ring on the top surface of the package substrate. At least two compartments are defined by the stiffener ring and the reinforcement rib. At least two individual chip packages are mounted on chip mounting regions within the at least two compartments, respectively, thereby constituting a package array on the package substrate.Type: GrantFiled: December 11, 2018Date of Patent: April 12, 2022Assignee: MediaTek Inc.Inventors: Chi-Wen Pan, I-Hsuan Peng, Sheng-Liang Kuo, Yi-Jou Lin, Tai-Yu Chen
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Publication number: 20220059577Abstract: A stretchable pixel array substrate, including a base and a component layer, is provided. The base has multiple first openings and multiple second openings. Each of the first openings has a first opening extending direction. Each of the second openings has a second opening extending direction. The first opening extending direction and the second opening extending direction are different. The first openings and the second openings are alternately arranged in a first direction and a second direction to define multiple islands and multiple bridges of the base. The component layer is disposed on the base and includes multiple island portions and multiple bridge portions. The island potions have multiple pixel structures and are respectively disposed on the islands of the base. The bridge portions have conductive wires and are respectively disposed on the bridges of the base. The conductive wires are electrically connected to the pixel structures.Type: ApplicationFiled: July 29, 2021Publication date: February 24, 2022Applicant: Au Optronics CorporationInventors: Yun-Wen Pan, Kung-Cheng Lin
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Patent number: 11164649Abstract: A test method for a memory device including the following steps is provided. A redundancy function of the memory device is disable and a first data is written to a first memory array. The redundancy function of the memory device is enabled and a second data is written to a second memory array. The first data and the second data are complementary. A redundancy information is read from a non-volatile memory block according to a margin condition and the second memory array is read based on the redundancy information to obtain a first readout data. A first test result is generated by comparing the second data and the first readout data. The second memory array includes a part of memory cells of the first memory array and at least one redundancy memory cell.Type: GrantFiled: April 20, 2020Date of Patent: November 2, 2021Assignee: Winbond Electronics Corp.Inventor: Tzi-Wen Pan
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Publication number: 20210327527Abstract: A test method for a memory device including the following steps is provided. A redundancy function of the memory device is disable and a first data is written to a first memory array. The redundancy function of the memory device is enabled and a second data is written to a second memory array. The first data and the second data are complementary. A redundancy information is read from a non-volatile memory block according to a margin condition and the second memory array is read based on the redundancy information to obtain a first readout data. A first test result is generated by comparing the second data and the first readout data. The second memory array includes a part of memory cells of the first memory array and at least one redundancy memory cell.Type: ApplicationFiled: April 20, 2020Publication date: October 21, 2021Applicant: Winbond Electronics Corp.Inventor: Tzi-Wen Pan
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Publication number: 20210280695Abstract: Methods of cutting fins, and structures formed thereby, are described. In an embodiment, a structure includes a first fin and a second fin on a substrate, and a fin cut-fill structure disposed between the first fin and the second fin. The first fin and the second fin are longitudinally aligned. The fin cut-fill structure includes a liner on a first sidewall of the first fin, and an insulating fill material on a sidewall of the liner and on a second sidewall of the first fin. The liner is further on a surface of the first fin between the first sidewall of the first fin and the second sidewall of the first fin.Type: ApplicationFiled: May 20, 2021Publication date: September 9, 2021Inventors: Ryan Chia-Jen Chen, Li-Wei Yin, Tzu-Wen Pan, Cheng-Chung Chang, Shao-Hua Hsu, Yi-Chun Chen, Yu-Hsien Lin, Ming-Ching Chang
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Patent number: 11114549Abstract: Methods of cutting fins, and structures formed thereby, are described. In an embodiment, a structure includes a first fin and a second fin on a substrate, and a fin cut-fill structure disposed between the first fin and the second fin. The first fin and the second fin are longitudinally aligned. The fin cut-fill structure includes a liner on a first sidewall of the first fin, and an insulating fill material on a sidewall of the liner and on a second sidewall of the first fin. The liner is further on a surface of the first fin between the first sidewall of the first fin and the second sidewall of the first fin.Type: GrantFiled: March 1, 2018Date of Patent: September 7, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ryan Chia-Jen Chen, Ming-Ching Chang, Yi-Chun Chen, Yu-Hsien Lin, Li-Wei Yin, Tzu-Wen Pan, Cheng-Chung Chang, Shao-Hua Hsu
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Publication number: 20210181821Abstract: The present invention provides a method of dynamic thermal management applied to a portable device, wherein the method includes the steps of: obtaining a surface temperature of the portable device; obtaining a junction temperature of a chip of the portable device; and calculating an upper limit of the junction temperature according to the junction temperature and the surface temperature.Type: ApplicationFiled: December 17, 2019Publication date: June 17, 2021Inventors: Pei-Yu Huang, Chih-Yuan Hsiao, Chiao-Pin Fan, Chi-Wen Pan, Tai-Yu Chen, Chien-Tse Fang, Jih-Ming Hsu, Yun-Ching Li
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Patent number: 10942067Abstract: The surface temperature of a portable device is estimated. The portable device includes a sensor for detecting the internal temperature of the portable device. The portable device also includes circuitry for estimating the surface temperature, using the internal temperature and an ambient temperature of the portable device as input to a circuit model. The circuit model describes thermal behaviors of the portable device. The circuitry is operative to identify a scenario in which the portable device operates, and determine the ambient temperature using the scenario and at least the internal temperature.Type: GrantFiled: July 3, 2020Date of Patent: March 9, 2021Assignee: MediaTek Inc.Inventors: Chi-Wen Pan, Pei-Yu Huang, Sheng-Liang Kuo, Jih-Ming Hsu, Tai-Yu Chen, Yun-Ching Li, Wei-Ting Wang
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Publication number: 20200333193Abstract: The surface temperature of a portable device is estimated. The portable device includes a sensor for detecting the internal temperature of the portable device. The portable device also includes circuitry for estimating the surface temperature, using the internal temperature and an ambient temperature of the portable device as input to a circuit model. The circuit model describes thermal behaviors of the portable device. The circuitry is operative to identify a scenario in which the portable device operates, and determine the ambient temperature using the scenario and at least the internal temperature.Type: ApplicationFiled: July 3, 2020Publication date: October 22, 2020Inventors: Chi-Wen Pan, Pei-Yu Huang, Sheng-Liang Kuo, Jih-Ming Hsu, Tai-Yu Chen, Yun-Ching Li, Wei-Ting Wang
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Patent number: 10770964Abstract: An overshoot reduction circuit for a buck converter includes an operational amplifier, a first sampler circuit, a pulse generator circuit, a pulse calculator circuit, a second sampler circuit and a comparator. The operational amplifier outputs an operation amplified signal according to a buck converted signal of the buck converter and a voltage feedback signal of the operational amplifier. The first sampler circuit samples a first capacitor voltage signal according to a lower bridge conducted signal of the buck converter. The pulse generator circuit outputs a pulse signal. The pulse calculator circuit outputs a first sample compared signal according to the first capacitor voltage signal and the pulse signal. The second sampler circuit samples a second capacitor voltage signal according to the lower bridge conducted signal. The comparator compares the second capacitor voltage signal with the first sample compared signal to output a comparing signal to the buck converter.Type: GrantFiled: July 22, 2019Date of Patent: September 8, 2020Assignee: ANPEC ELECTRONICS CORPORATIONInventors: Chih-Heng Su, Sheng-Wen Pan
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Patent number: 10739206Abstract: The surface temperature of a portable device is estimated. A sensor detects the internal temperature of the portable device. The internal temperature and an ambient temperature are used as input to a circuit model that describes thermal behaviors of the portable device. Dynamic thermal management may be performed based on the estimated surface temperature.Type: GrantFiled: December 30, 2017Date of Patent: August 11, 2020Assignee: MediaTek Inc.Inventors: Chi-Wen Pan, Pei-Yu Huang, Sheng-Liang Kuo, Jih-Ming Hsu, Tai-Yu Chen, Yun-Ching Li, Wei-Ting Wang
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Patent number: 10573579Abstract: A semiconductor package includes a package substrate having a top surface and a bottom surface, an interposer mounted on the top surface of the package substrate, a first semiconductor die and a second semiconductor die mounted on the interposer in a side-by-side manner, and a stiffener ring secured to the top surface of the package substrate. The stiffener ring encircles the first semiconductor die and the second semiconductor die. The stiffener ring comprises a reinforcement rib striding across the interposer.Type: GrantFiled: January 8, 2018Date of Patent: February 25, 2020Assignee: MEDIATEK INC.Inventors: Tai-Yu Chen, Wen-Sung Hsu, Sheng-Liang Kuo, Chi-Wen Pan, Jen-Chuan Chen
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Patent number: 10325912Abstract: Methods of cutting gate structures and fins, and structures formed thereby, are described. In an embodiment, a substrate includes first and second fins and an isolation region. The first and second fins extend longitudinally parallel, with the isolation region disposed therebetween. A gate structure includes a conformal gate dielectric over the first fin and a gate electrode over the conformal gate dielectric. A first insulating fill structure abuts the gate structure and extends vertically from a level of an upper surface of the gate structure to at least a surface of the isolation region. No portion of the conformal gate dielectric extends vertically between the first insulating fill structure and the gate electrode. A second insulating fill structure abuts the first insulating fill structure and an end sidewall of the second fin. The first insulating fill structure is disposed laterally between the gate structure and the second insulating fill structure.Type: GrantFiled: October 30, 2017Date of Patent: June 18, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ryan Chia-Jen Chen, Li-Wei Yin, Tzu-Wen Pan, Yi-Chun Chen, Cheng-Chung Chang, Shao-Hua Hsu, Yu-Hsien Lin, Ming-Ching Chang
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Publication number: 20190165137Abstract: Methods of cutting fins, and structures formed thereby, are described. In an embodiment, a structure includes a first fin and a second fin on a substrate, and a fin cut-fill structure disposed between the first fin and the second fin. The first fin and the second fin are longitudinally aligned. The fin cut-fill structure includes a liner on a first sidewall of the first fin, and an insulating fill material on a sidewall of the liner and on a second sidewall of the first fin. The liner is further on a surface of the first fin between the first sidewall of the first fin and the second sidewall of the first fin.Type: ApplicationFiled: March 1, 2018Publication date: May 30, 2019Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ryan Chia-Jen CHEN, Ming-Ching CHANG, Yi-Chun CHEN, Yu-Hsien LIN, Li-Wei YIN, Tzu-Wen PAN, Cheng-Chung CHANG, Shao-Hua HSU
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Publication number: 20190131297Abstract: Methods of cutting gate structures and fins, and structures formed thereby, are described. In an embodiment, a substrate includes first and second fins and an isolation region. The first and second fins extend longitudinally parallel, with the isolation region disposed therebetween. A gate structure includes a conformal gate dielectric over the first fin and a gate electrode over the conformal gate dielectric. A first insulating fill structure abuts the gate structure and extends vertically from a level of an upper surface of the gate structure to at least a surface of the isolation region. No portion of the conformal gate dielectric extends vertically between the first insulating fill structure and the gate electrode. A second insulating fill structure abuts the first insulating fill structure and an end sidewall of the second fin. The first insulating fill structure is disposed laterally between the gate structure and the second insulating fill structure.Type: ApplicationFiled: October 30, 2017Publication date: May 2, 2019Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: RYAN CHIA-JEN CHEN, LI-WEI YIN, TZU-WEN PAN, YI-CHUN CHEN, CHENG-CHUNG CHANG, SHAO-HUA HSU, YU-HSIEN LIN, MING-CHING CHANG
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Patent number: D906715Type: GrantFiled: October 12, 2019Date of Patent: January 5, 2021Inventors: Wen Pan, Changtao Yang