Patents by Inventor Wen-Pin Huang

Wen-Pin Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11967546
    Abstract: A semiconductor structure includes a first interposer; a second interposer laterally adjacent to the first interposer, where the second interposer is spaced apart from the first interposer; and a first die attached to a first side of the first interposer and attached to a first side of the second interposer, where the first side of the first interposer and the first side of the second interposer face the first die.
    Type: Grant
    Filed: July 21, 2022
    Date of Patent: April 23, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shang-Yun Hou, Hsien-Pin Hu, Sao-Ling Chiu, Wen-Hsin Wei, Ping-Kang Huang, Chih-Ta Shen, Szu-Wei Lu, Ying-Ching Shih, Wen-Chih Chiou, Chi-Hsi Wu, Chen-Hua Yu
  • Publication number: 20240102504
    Abstract: A fastener includes a bolt including a head and a threaded shank including a bare section proximate the head, a threaded end section, an intermediate section proximate the threaded end section and having a spiral trough, and a threaded section between the intermediate section and the bare section; and a hollow member including a head member and a malleable shank. The malleable shank has first, second and third holes.
    Type: Application
    Filed: November 1, 2023
    Publication date: March 28, 2024
    Inventor: Wen-Pin Huang
  • Publication number: 20240096861
    Abstract: A semiconductor package assembly is provided. The semiconductor package assembly includes first semiconductor die, a second semiconductor die and a memory package. The first semiconductor die and the second semiconductor die are stacked on each other. The first semiconductor die includes a first interface and a third interface. The first interface overlaps and is electrically connected to the second interface arranged on the second semiconductor die. The third interface is arranged on a first edge of the first semiconductor die. The memory package is disposed beside the first semiconductor die, wherein the memory package is electrically connected to the first semiconductor die by the third interface.
    Type: Application
    Filed: August 23, 2023
    Publication date: March 21, 2024
    Inventors: Che-Hung KUO, Hsiao-Yun CHEN, Wen-Pin CHU, Chun-Hsiang HUANG
  • Publication number: 20240084838
    Abstract: A fastener includes a bolt including a head and a threaded shank having a conic, bare section proximate the head, a threaded section having a plurality of annular ridges and a plurality of spiral grooves in the annular ridges; and a hollow member including a head and a shank. The hollow member is configured to dispose on the bolt with an end of the shank being urged by the conic, bare section. The spiral grooves are spaced apart 90-degree each other.
    Type: Application
    Filed: October 16, 2023
    Publication date: March 14, 2024
    Inventor: Wen-Pin Huang
  • Publication number: 20240084839
    Abstract: A fastener includes a bolt including a head, a threaded shank having a bare section proximate the head, an intermediate grooved section, and an end section; and a hollow member including a head and a malleable shank having a plurality of holes through the shank. The grooved section includes a plurality of longitudinal grooves and a plurality of arcuate troughs between two of the adjacent grooves. The end section includes a plurality of projections arranged in a plurality of spaced, annular sets, and a plurality of cavities arranged in a plurality of spaced, annular sets. Each cavity is disposed between two of the adjacent projections. Each projection is disposed between two of the adjacent cavities.
    Type: Application
    Filed: October 17, 2023
    Publication date: March 14, 2024
    Inventor: Wen-Pin Huang
  • Patent number: 11913733
    Abstract: The present disclosure provides a heat transferring device and a heat transferring component thereof. The heat transferring device includes a heat transferring component, a lower plate and a positioning component. The heat transferring component is in a shape of pouch and includes at least one input end and at least one output end to allow a fluid to be inputted and outputted. The lower plate includes at least one first perforation. The positioning component is disposed on an exterior of the heat transferring component. An end of the positioning component is connected to the lower plate.
    Type: Grant
    Filed: June 10, 2021
    Date of Patent: February 27, 2024
    Assignee: ASIA PACIFIC FUEL CELL TECHNOLOGIES, LTD.
    Inventors: Wei-Pin Lo, Wen-Yen Huang, Chin-Hsien Cheng
  • Publication number: 20240011521
    Abstract: A fastening device includes a reverse self-tapping screw including a nut and a threaded shank having a tapered section and a threaded section wherein the tapered section is a reverse self-tapping screw formed on the threaded shank adjacent to the nut and has a length of d/4 to d/3; the reverse self-tapping screw is a screw having a tapered surface of 1.5×d/16; and the threaded section is a forward threaded screw; and an anti-loosening assembly including an internally threaded fastening element and a retaining ring. The internally threaded fastening element includes a nut member and an anti-loosening member having a plurality of spiral constriction grooves. The spiral constriction grooves have an inclined angle of 30°-60° with respect to an axis thereof, and an annular groove for securely receiving the retaining ring.
    Type: Application
    Filed: August 31, 2023
    Publication date: January 11, 2024
    Inventor: Wen-Pin Huang
  • Patent number: 11823850
    Abstract: An information handling system keyboard backlight illuminates with a single mini-LED disposed under each of plural keyboard keys and having a penta directional illumination that illuminates directly at the key and coplanar a light guide material around the perimeter of the mini-LED. The light guide material in cooperation with a reflector below and a mask above provides indirect illumination at the periphery of the key for a more uniform key illumination. A substrate carried with circuits below the mini-LED powers the mini-LED so that a more bulky flexible printed circuit is not needed.
    Type: Grant
    Filed: October 28, 2022
    Date of Patent: November 21, 2023
    Assignee: Dell Products L.P.
    Inventors: Wen-Pin Huang, Hsien-Tsan Chang, Yi-Chen Wang, Po-Chun Hou
  • Publication number: 20230356284
    Abstract: A manufacturing process includes drilling a hole through a polyhedron; cutting a first surface from an outer surface of the polyhedron to the hole and subsequently clockwise cutting the outer surface of the polyhedron until the cutting meets a bottom edge of the first surface to form first and second nuts; rotating the first nut with about the second nut along the spiral cut surface to separate the first nut from the second nut, thereby forming a second surface, increasing height of the polyhedron, and forming a gap from the first surface to the second surface between the first nut and the second nut; fastening the first and second nuts together by spot welding; and disposing a sleeve on the polyhedron and driving a tap through the axial hole to create female threads in the first and second nuts respectively. An eccentric, internally threaded fastener is finished.
    Type: Application
    Filed: July 21, 2023
    Publication date: November 9, 2023
    Inventor: Wen-Pin Huang
  • Patent number: 11791280
    Abstract: A semiconductor device package includes a substrate, a first electronic component, a second electronic component, a package body and a shield. The substrate has a first surface and a second surface opposite to the first surface. The substrate defines a cavity from the second surface extending into the substrate. The first electronic component is disposed on the first surface of the substrate. The second electronic component is disposed within the cavity of the substrate. The package body is disposed on a portion of the first surface of the substrate and covers the first electronic component. The shield is disposed on external surfaces of the package body.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: October 17, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Li-Hua Tai, Pai-Chou Liu, Yun-Chih Fei, Wen-Pin Huang, Sheng-Hong Zheng
  • Publication number: 20230197487
    Abstract: A wafer supporting mechanism and a method for wafer dicing are provided. The wafer supporting mechanism includes a base portion and a support portion. The base portion includes a first gas channel and a first outlet connected to the first gas channel. The support portion is connected to the base portion and including a second gas channel connected to the first gas channel. An accommodation space is defined by the base portion and the support portion.
    Type: Application
    Filed: February 21, 2023
    Publication date: June 22, 2023
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Bo Hua CHEN, Yan Ting SHEN, Fu Tang CHU, Wen-Pin HUANG
  • Publication number: 20230160414
    Abstract: An eccentric anti-loosening screw device includes a screw and a fastening assembly. The screw includes a head and a threaded shank. The fastening assembly is threadedly secured onto the shank and includes first and second locking members each including a longitudinal threaded hole secured onto the shank, and a surface of curved inclination on an end with the threaded hole passing through; and an angle of curved inclination is greater than a pitch of the shank. The surface of curved inclination of the first locking member is engaged with that of the second locking member to form a gap therebetween. Solder points fasten the first and second locking members together. A rotation of the first locking member about the second locking member fastens the first and second locking members together, and the second locking member is further rotated until the solder points are broken to generate an eccentric force.
    Type: Application
    Filed: August 22, 2022
    Publication date: May 25, 2023
    Inventor: Wen-Pin Huang
  • Patent number: 11637055
    Abstract: The present disclosure provides a semiconductor device package. The semiconductor device package includes a first substrate and a second substrate. The first substrate has a first surface and a second surface opposite to the first surface of the first substrate. The second substrate has a first surface facing the first substrate and a second surface opposite to the first surface of the second substrate. The semiconductor device package also includes a first electronic component disposed on the first surface of the second substrate and electrically connected to the first surface of the second substrate. The semiconductor device package also includes a first encapsulant and a second encapsulant between the first substrate and the second substrate. The first encapsulant is different from the second encapsulant. A method of manufacturing a semiconductor device package is also disclosed.
    Type: Grant
    Filed: August 3, 2020
    Date of Patent: April 25, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Li-Hua Tai, Wen-Pin Huang
  • Publication number: 20230106612
    Abstract: A method for manufacturing an electrical package is provided. The method include: providing a substrate having a first surface and a second surface opposite to the first surface, wherein the second surface has a first level difference; forming an adhesive layer on the second surface of the substrate, wherein the adhesive layer is configured to cover the second surface and provides a third surface spaced apart from the second surface of the substrate, wherein the third surface has a second level difference; disposing a tape on the third surface of the adhesive layer; and performing a removing operation on the first surface of the substrate; wherein the second level difference is smaller than the first level difference.
    Type: Application
    Filed: October 5, 2021
    Publication date: April 6, 2023
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Wen-Pin HUANG, Fu Tang CHU, Pei I CHANG, Chia Hao CHEN, Tsuan Ching KUO
  • Patent number: 11587809
    Abstract: A wafer supporting mechanism and a method for wafer dicing are provided. The wafer supporting mechanism includes a base portion and a support portion. The base portion includes a first gas channel and a first outlet connected to the first gas channel. The support portion is connected to the base portion and including a second gas channel connected to the first gas channel. An accommodation space is defined by the base portion and the support portion.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: February 21, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Bo Hua Chen, Yan Ting Shen, Fu Tang Chu, Wen-Pin Huang
  • Publication number: 20220102176
    Abstract: A wafer supporting mechanism and a method for wafer dicing are provided. The wafer supporting mechanism includes a base portion and a support portion. The base portion includes a first gas channel and a first outlet connected to the first gas channel. The support portion is connected to the base portion and including a second gas channel connected to the first gas channel. An accommodation space is defined by the base portion and the support portion.
    Type: Application
    Filed: September 30, 2020
    Publication date: March 31, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Bo Hua CHEN, Yan Ting SHEN, Fu Tang CHU, Wen-Pin HUANG
  • Publication number: 20220077347
    Abstract: Disclosed is a multi-quantum well structure including a stress relief layer, an electron-collecting layer disposed on the stress relief layer, and an active layer including a first active layer unit that is disposed on the electron-collecting layer. The first active layer unit includes potential barrier sub-layers and potential well sub-lavers being alternately stacked, in which at least one of the potential barrier sub-layers has a GaN/Alx1Iny1Ga(1-x1-y1)N stack, where 0<x1?1 and 0?y1<1. An LED device including the multi-quantum well structure is also disclosed.
    Type: Application
    Filed: November 17, 2021
    Publication date: March 10, 2022
    Inventors: HAN JIANG, YUNG-LING LAN, WEN-PIN HUANG, CHANGWEI SONG, LI-CHENG HUANG, FEILIN XUN, CHAN-CHAN LING, CHI-MING TSAI, CHIA-HUNG CHANG
  • Publication number: 20220037244
    Abstract: The present disclosure provides a semiconductor device package. The semiconductor device package includes a first substrate and a second substrate. The first substrate has a first surface and a second surface opposite to the first surface of the first substrate. The second substrate has a first surface facing the first substrate and a second surface opposite to the first surface of the second substrate. The semiconductor device package also includes a first electronic component disposed on the first surface of the second substrate and electrically connected to the first surface of the second substrate. The semiconductor device package also includes a first encapsulant and a second encapsulant between the first substrate and the second substrate. The first encapsulant is different from the second encapsulant. A method of manufacturing a semiconductor device package is also disclosed.
    Type: Application
    Filed: August 3, 2020
    Publication date: February 3, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Li-Hua TAI, Wen-Pin HUANG
  • Publication number: 20210391278
    Abstract: A semiconductor device package includes a substrate, a first electronic component, a second electronic component, a package body and a shield. The substrate has a first surface and a second surface opposite to the first surface. The substrate defines a cavity from the second surface extending into the substrate. The first electronic component is disposed on the first surface of the substrate. The second electronic component is disposed within the cavity of the substrate. The package body is disposed on a portion of the first surface of the substrate and covers the first electronic component. The shield is disposed on external surfaces of the package body.
    Type: Application
    Filed: August 30, 2021
    Publication date: December 16, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Li-Hua TAI, Pai-Chou LIU, Yun-Chih FEI, Wen-Pin HUANG, Sheng-Hong ZHENG
  • Patent number: 11189751
    Abstract: Disclosed is a multi-quantum well structure including a stress relief layer, an electron-collecting layer disposed on the stress relief layer, and an active layer including a first active layer unit that is disposed on the electron-collecting layer. The first active layer unit includes potential barrier sub-layers and potential well sub-layers being alternately stacked, in which at least one of the potential barrier sub-layers has a GaN/Alx1Iny1Ga(1-x1-y1)N/GaN stack, where 0<x1?1 and 0?y1<1, and for the remainder of the potential barrier sub-layers, each of the potential barrier sub-layers is a GaN layer. An LED device including the multi-quantum well structure is also disclosed.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: November 30, 2021
    Assignee: Xiamen San'An Optoelectronics Co., Ltd.
    Inventors: Han Jiang, Yung-Ling Lan, Wen-Pin Huang, Changwei Song, Li-Cheng Huang, Feilin Xun, Chan-Chan Ling, Chi-Ming Tsai, Chia-Hung Chang