Patents by Inventor Wen-Shiang Liao

Wen-Shiang Liao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230341624
    Abstract: An integrated optical device includes a substrate, a waveguide structure and a grating structure. The substrate has a waveguide region and a grating region adjacent to each other. The waveguide structure is disposed on the substrate in the waveguide region. The grating structure is disposed on the substrate in the grating region. In some embodiments, the grating structure includes grating bars and grating intervals arranged alternately, and widths of the grating bars of the grating structure are varied.
    Type: Application
    Filed: April 21, 2022
    Publication date: October 26, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Feng-Wei Kuo, Wen-Shiang Liao
  • Publication number: 20230335884
    Abstract: A semiconductor package includes a semiconductor die, an encapsulation layer and at least one antenna structure. The encapsulation layer laterally encapsulates the semiconductor die. The at least one antenna structure is embedded in the encapsulation layer aside the semiconductor die. The at least one antenna structure includes a dielectric bulk, and a dielectric constant of the dielectric bulk is higher than a dielectric constant of the encapsulation layer.
    Type: Application
    Filed: June 18, 2023
    Publication date: October 19, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Wen-Shiang Liao
  • Patent number: 11791534
    Abstract: This application relates to a device for signal transmission (e.g., radio frequency transmission) and a method for forming the device. For example, the method includes: depositing an insulating layer that includes polybenzobisoxazole (PBO) on a carrier; forming a backside layer including polyimide (PI) over the adhesive layer; forming a die-attach film (DAF) over the backside layer; forming one or more through-insulator via (TIV)-wall structures and one or more TIV-grating structures on the second backside layer; placing a die, such as a radio frequency (RF) integrated circuit (IC) die, on the DAF; encapsulating the die, the one or more TIV-wall structures, and the one or more TIV-grating structures, with a molding compound to form an antenna package including one or more antenna regions; and forming a redistribution layer (RDL) structure on the encapsulated package. The RDL structure can include one or more antenna structures coupled to the die.
    Type: Grant
    Filed: August 3, 2021
    Date of Patent: October 17, 2023
    Assignee: Tawian Semiconductor Manufacturing Co., Ltd.
    Inventors: Feng-Wei Kuo, Wen-Shiang Liao
  • Publication number: 20230324615
    Abstract: Disclosed are apparatuses for optical coupling and a system for communication. In one embodiment, an apparatus for optical coupling including a substrate and a grating coupler is disclosed. The grating coupler is disposed on the substrate and includes a plurality of coupling gratings arranged along a first direction, wherein effective refractive indices of the plurality of coupling gratings gradually decrease along the first direction.
    Type: Application
    Filed: June 14, 2023
    Publication date: October 12, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Feng-Wei Kuo, Wen-Shiang Liao, Robert Bogdan Staszewski, Jianglin Du
  • Publication number: 20230307390
    Abstract: A semiconductor package includes a first semiconductor device, a second semiconductor device vertically positioned above the first semiconductor device, and a ground shielded transmission path. The ground shielded transmission path couples the first semiconductor device to the second semiconductor device. The ground shielded transmission path includes a first signal path extending longitudinally between a first end and a second end. The first signal path includes a conductive material. A first insulating layer is disposed over the signal path longitudinally between the first end and the second end. The first insulating layer includes an electrically insulating material. A ground shielding layer is disposed over the insulating material longitudinally between the first end and the second end of the signal path. The ground shielding layer includes a conductive material coupled to ground.
    Type: Application
    Filed: March 21, 2023
    Publication date: September 28, 2023
    Inventors: Feng Wei KUO, Wen-Shiang Liao, Chewn-Pu Jou, Huan-Neng Chen, Lan-Chou Cho, William Wu Shen
  • Publication number: 20230298993
    Abstract: Among other things, a method of fabricating an integrated electronic device package is described. First trace portions of an electrically conductive trace are formed on an electrically insulating layer of a package structure, and vias of the conductive trace are formed in a sacrificial layer disposed on the electrically insulating layer. The sacrificial layer is removed, and a die is placed above the electrically insulating layer. Molding material is formed around exposed surfaces of the die and exposed surfaces of the vias, and a magnetic structure is formed within the layer of molding material. Second trace portions of the electrically conductive trace are formed above the molding material and the magnetic structure. The electrically conductive trace and the magnetic structure form an inductor. The electrically conductive trace may have a coil shape surrounding the magnetic structure. The die may be positioned between portions of the inductor.
    Type: Application
    Filed: May 25, 2023
    Publication date: September 21, 2023
    Inventors: Wen-Shiang Liao, Chih-Hang Tung, Chen-Hua Yu, Chewn-Pu Jou, Feng Wei Kuo
  • Patent number: 11764173
    Abstract: A semiconductor structure includes: a substrate; a first dielectric layer over the substrate; a waveguide over the first dielectric layer; a second dielectric layer over the first dielectric layer and laterally surrounding the waveguide; a first conductive member and a second conductive member over the second dielectric layer and the waveguide, the first conductive member and the second conductive member being in contact with the waveguide; a conductive bump on one side of the substrate and electrically connected to the first conductive member or the second conductive member; and a conductive via extending through the substrate and electrically connecting the conductive bump to the first conductive member or the second conductive member. The waveguide is configured to transmit an electromagnetic signal between the first conductive member and the second conductive member.
    Type: Grant
    Filed: June 30, 2022
    Date of Patent: September 19, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Huan-Neng Chen, Wen-Shiang Liao
  • Patent number: 11749625
    Abstract: A semiconductor structure includes a first redistribution structure, wherein the first redistribution structure includes first conductive pattern. The semiconductor structure further includes a die over the first redistribution structure. The semiconductor structure further includes a molding over the first redistribution structure, wherein the molding surrounds the die, and the molding has a first dielectric constant. The semiconductor structure further includes a dielectric member extending through the molding, wherein the dielectric member has a second dielectric constant different from the first dielectric constant. The semiconductor structure further includes a second redistribution structure over the die, the dielectric member and the molding, wherein the second redistribution layer includes an antenna over the dielectric member, and the antenna is electrically connected to the die.
    Type: Grant
    Filed: December 10, 2020
    Date of Patent: September 5, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Feng-Wei Kuo, Wen-Shiang Liao
  • Publication number: 20230275045
    Abstract: A method includes: forming an interconnect structure over a semiconductor substrate. The interconnect structure includes: a magnetic core and a conductive coil winding around the magnetic core and electrically insulated from the magnetic core. The conductive coil includes horizontally-extending conductive lines and vertically-extending conductive vias electrically connecting the horizontally-extending conductive lines, wherein the magnetic core and the conductive coil are arranged in an inductor zone of the interconnect structure; and a connecting metal line adjacent to and on an outside of the inductor zone, the connecting metal line being electrical isolated from the inductor zone. The vertically-extending conductive vias include first conductive vias, second conductive vias, and a third conductive via between the first conductive vias and the second conductive vias.
    Type: Application
    Filed: May 10, 2023
    Publication date: August 31, 2023
    Inventors: WEN-SHIANG LIAO, HUAN-NENG CHEN
  • Publication number: 20230268298
    Abstract: A method of forming a semiconductor structure includes: providing a first inter-level dielectric (ILD) layer overlying a molding layer, the molding layer including a transmitter ground structure and a receiver ground structure; forming first openings through the first ILD layer to expose the transmitter and receiver ground structures; forming first lower transmitter and receiver electrodes in the first openings to be respectively coupled to the transmitter and receiver ground structures; forming a first dielectric waveguide overlying the first ILD layer, and first lower transmitter and receiver electrodes; depositing a second ILD layer overlying the first dielectric waveguide; forming second lower transmitter and receiver electrodes extending through the second ILD and respectively coupled to the transmitter and receiver ground structures; and forming a second dielectric waveguide overlying the second ILD layer and the second lower transmitter and receiver electrodes.
    Type: Application
    Filed: May 2, 2023
    Publication date: August 24, 2023
    Inventors: WEN-SHIANG LIAO, HUAN-NENG CHEN
  • Publication number: 20230260872
    Abstract: A semiconductor package includes a semiconductor substrate, a plurality of first dies, a plurality of thermal conductive patterns and an interposer. The first dies are bonded to the semiconductor substrate. The thermal conductive patterns are bonded to the semiconductor substrate. The interposer is bonded to the first dies, and the first dies and the thermal conductive patterns are disposed between the semiconductor substrate and the interposer.
    Type: Application
    Filed: February 16, 2022
    Publication date: August 17, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Shiang Liao, Chieh-Yen Chen, Chuei-Tang Wang
  • Publication number: 20230261037
    Abstract: A package includes a first redistribution structure, a second redistribution structure, an inductor, a permalloy core, and a die. The second redistribution structure is over the first redistribution structure. The inductor includes a first portion, a second portion, and a third portion. The first portion is embedded in the first redistribution structure, the third portion is embedded in the second redistribution structure, and the second portion connects the first and third portions of the inductor. The permalloy core is located between the first and third portions of the inductor. The die is disposed adjacent to the second portion of the inductor.
    Type: Application
    Filed: April 24, 2023
    Publication date: August 17, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Shiang Liao, Chih-Hang Tung
  • Publication number: 20230258886
    Abstract: A package structure including a wiring substrate, an interposer and a semiconductor die is provided. The interposer is disposed on and electrically connected to the wiring substrate, and the interposer includes an embedded dielectric waveguide. The semiconductor die is disposed on and electrically connected to the interposer. In some embodiments, the interposer includes a semiconductor substrate; dielectric layers stacked on the semiconductor substrate; and conductive wirings disposed on and electrically connected to the semiconductor substrate, wherein the conductive wirings and the embedded dielectric waveguide are embedded in the dielectric layers.
    Type: Application
    Filed: February 16, 2022
    Publication date: August 17, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Shiang Liao, Hsien-Wei Chen
  • Patent number: 11728291
    Abstract: A semiconductor arrangement in fan out packaging has a molding compound adjacent a side of a semiconductor die. A magnetic structure is disposed above the molding compound, above the semiconductor die, and around a transmission line coupled to an integrated circuit of the semiconductor die. The magnetic structure has a top magnetic portion, a bottom magnetic portion, a first side magnetic portion, and a second side magnetic portion. The first side magnetic portion and the second side magnetic portion are coupled to the top magnetic portion and to the bottom magnetic portion. The first side magnetic portion and the second side magnetic portion have tapered sidewalls.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: August 15, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Wen-Shiang Liao, Huan-Neng Chen
  • Patent number: 11719885
    Abstract: Disclosed are apparatuses for optical coupling and a system for communication. In one embodiment, an apparatus for optical coupling including a substrate and a grating coupler is disclosed. The grating coupler is disposed on the substrate and includes a plurality of coupling gratings arranged along a first direction, wherein effective refractive indices of the plurality of coupling gratings gradually decrease along the first direction.
    Type: Grant
    Filed: October 14, 2020
    Date of Patent: August 8, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Feng-Wei Kuo, Wen-Shiang Liao, Robert Bogdan Staszewski, Jianglin Du
  • Patent number: 11721883
    Abstract: A semiconductor package includes a semiconductor die, an encapsulation layer and at least one antenna structure. The encapsulation layer laterally encapsulates the semiconductor die. The at least one antenna structure is embedded in the encapsulation layer aside the semiconductor die. The at least one antenna structure includes a dielectric bulk, and a dielectric constant of the dielectric bulk is higher than a dielectric constant of the encapsulation layer.
    Type: Grant
    Filed: February 25, 2021
    Date of Patent: August 8, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Wen-Shiang Liao
  • Publication number: 20230230970
    Abstract: A package having a capacitor structure and a method of forming the same are provided. The package includes a first die; a second die bonded onto the first die; an isolation region disposed on the first die and laterally encapsulating the second die; at least one first through-via disposed aside the second die and penetrating through the isolation region; an electrode layer disposed on the at least one first through-via; and a capacitor dielectric layer disposed between the at least one first through-via and the electrode layer to separate the at least one first through-via from the electrode layer, wherein the at least one first through-via, the capacitor dielectric layer, and the electrode layer constitute a capacitor structure.
    Type: Application
    Filed: January 19, 2022
    Publication date: July 20, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Wen-Shiang Liao
  • Publication number: 20230221488
    Abstract: A thermally tunable waveguide including an optical waveguide and a heater is provided. The optical waveguide includes a phase shifter. The heater is disposed over the optical waveguide. The heater includes a heating portion, pad portions and tapered portions. The heating portion overlaps with the phase shifter of the optical waveguide. The pad portions are disposed aside of the heating portion. Each of the pad portions is connected to the heating portion through one of the tapered portions respectively.
    Type: Application
    Filed: January 11, 2022
    Publication date: July 13, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Feng-Wei Kuo, Wen-Shiang Liao
  • Patent number: 11699669
    Abstract: A method includes: forming an interconnect structure over a semiconductor substrate. The interconnect structure includes: a magnetic core and a conductive coil winding around the magnetic core and electrically insulated from the magnetic core, wherein the conductive coil has horizontally-extending conductive lines and vertically-extending conductive vias electrically connecting the horizontally-extending conductive lines, wherein the magnetic core and the conductive coil are arranged in an inductor zone of the interconnect structure. The interconnect structure also includes a dielectric material electrically insulating the magnetic core from the conductive coil, and a connecting metal line adjacent to and on the outside of the inductor zone. The connecting metal line is electrical isolated from the inductor zone. The connecting metal line includes an upper surface lower than an upper surface of the second conductive vias and a bottom surface higher than a bottom surface of the first conductive vias.
    Type: Grant
    Filed: June 26, 2022
    Date of Patent: July 11, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Wen-Shiang Liao, Huan-Neng Chen
  • Patent number: 11688685
    Abstract: Among other things, a method of fabricating an integrated electronic device package is described. First trace portions of an electrically conductive trace are formed on an electrically insulating layer of a package structure, and vias of the conductive trace are formed in a sacrificial layer disposed on the electrically insulating layer. The sacrificial layer is removed, and a die is placed above the electrically insulating layer. Molding material is formed around exposed surfaces of the die and exposed surfaces of the vias, and a magnetic structure is formed within the layer of molding material. Second trace portions of the electrically conductive trace are formed above the molding material and the magnetic structure. The electrically conductive trace and the magnetic structure form an inductor. The electrically conductive trace may have a coil shape surrounding the magnetic structure. The die may be positioned between portions of the inductor.
    Type: Grant
    Filed: February 4, 2021
    Date of Patent: June 27, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Wen-Shiang Liao, Chih-Hang Tung, Chen-Hua Yu, Chewn-Pu Jou, Feng Wei Kuo