Patents by Inventor Wen-Shiang Liao
Wen-Shiang Liao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240369770Abstract: Disclosed are apparatuses for optical coupling and a system for communication. In one embodiment, an apparatus for optical coupling including a substrate and a grating coupler is disclosed. The grating coupler is disposed on the substrate and includes a plurality of coupling gratings arranged along a first direction, wherein effective refractive indices of the plurality of coupling gratings gradually decrease along the first direction.Type: ApplicationFiled: July 15, 2024Publication date: November 7, 2024Inventors: Feng-Wei Kuo, Wen-Shiang Liao, Robert Bogdan Staszewski, Jianglin Du
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Publication number: 20240371916Abstract: A package includes a die, an inductor, and a permalloy core. The die has an active surface and a rear surface opposite to the active surface. The inductor includes a first portion, a second portion, and a third portion. The first portion is above the active surface of the die. The third portion is below the rear surface of the die. The second portion is aside the die. The second portion connects the first and third portions of the inductor. The permalloy core is located between the first and third portions of the inductor.Type: ApplicationFiled: July 22, 2024Publication date: November 7, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wen-Shiang Liao, Chih-Hang Tung
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Publication number: 20240363560Abstract: A semiconductor package includes a first semiconductor device, a second semiconductor device vertically positioned above the first semiconductor device, and a ground shielded transmission path. The ground shielded transmission path couples the first semiconductor device to the second semiconductor device. The ground shielded transmission path includes a first signal path extending longitudinally between a first end and a second end. The first signal path includes a conductive material. A first insulating layer is disposed over the signal path longitudinally between the first end and the second end. The first insulating layer includes an electrically insulating material. A ground shielding layer is disposed over the insulating material longitudinally between the first end and the second end of the signal path. The ground shielding layer includes a conductive material coupled to ground.Type: ApplicationFiled: July 8, 2024Publication date: October 31, 2024Inventors: Feng Wei KUO, Wen-Shiang LIAO, Chewn-Pu JOU, Huan-Neng CHEN, Lan-Chou CHO, William Wu SHEN
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Publication number: 20240363505Abstract: The present disclosure is directed to a method for forming metal insulator metal decoupling capacitors with scalable capacitance. The method can include forming a first redistribution layer with metal lines on a portion of a polymer layer, depositing a photoresist layer on the first redistribution layer, and etching the photoresist layer to form spaced apart first and second TIV openings in the photoresist layer, where the first TIV opening is wider than the second TIV opening. The method can further include depositing a metal in the first and second TIV openings to form respective first and second TIV structures in contact with the metal line, removing the photoresist layer, forming a high-k dielectric on a top surface of the first and second TIV structures, and depositing a metal layer on the high-k dielectric layer to form respective first and second capacitors.Type: ApplicationFiled: July 8, 2024Publication date: October 31, 2024Applicant: Taiwan Semicondutor Manufacturing Company, Ltd.Inventors: Feng-Wei KUO, Wen-Shiang Liao
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Publication number: 20240361527Abstract: An integrated optical device includes a substrate, a waveguide structure and a grating structure. The substrate has a waveguide region and a grating region adjacent to each other. The waveguide structure is disposed on the substrate in the waveguide region. The grating structure is disposed on the substrate in the grating region. In some embodiments, the grating structure includes grating bars and grating intervals arranged alternately, and widths of the grating bars of the grating structure are varied.Type: ApplicationFiled: July 9, 2024Publication date: October 31, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Feng-Wei Kuo, Wen-Shiang Liao
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Patent number: 12132074Abstract: A package includes a first redistribution structure, a second redistribution structure, an inductor, a permalloy core, and a die. The second redistribution structure is over the first redistribution structure. The inductor includes a first portion, a second portion, and a third portion. The first portion is embedded in the first redistribution structure, the third portion is embedded in the second redistribution structure, and the second portion connects the first and third portions of the inductor. The permalloy core is located between the first and third portions of the inductor. The die is disposed adjacent to the second portion of the inductor.Type: GrantFiled: April 24, 2023Date of Patent: October 29, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wen-Shiang Liao, Chih-Hang Tung
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Publication number: 20240355720Abstract: A method of manufacturing a semiconductor device is provided. A permalloy device is received. An interposer die is formed. A conductive coil is formed over a substrate, and the conductive coil includes a bottom metal layer over the substrate, a middle metal layer and a top metal layer interconnected to each other. The permalloy device is disposed in the middle metal layer through a pick and place operation before forming the top metal layer of the conductive coil. A semiconductor die is bonded to the interposer die. The permalloy device has a polygonal ring shape wrapped with the conductive coil.Type: ApplicationFiled: June 17, 2024Publication date: October 24, 2024Inventors: YING-CHIH HSU, WEN-SHIANG LIAO
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Publication number: 20240339369Abstract: A package structure and a formation method of a package structure are provided. The method includes surrounding a semiconductor chip with a protective layer. The protective layer has a first dielectric constant. The method also includes partially removing the protective layer to form an opening. The method further includes forming a dielectric structure partially or completely filling the opening. The dielectric structure has a second dielectric constant, and the second dielectric constant is higher than the first dielectric constant. The method further includes forming a redistribution structure over the semiconductor chip, the protective layer, and the dielectric structure.Type: ApplicationFiled: April 10, 2023Publication date: October 10, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Wen-Shiang LIAO
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Publication number: 20240329304Abstract: An optical attenuating structure is provided. The optical attenuating structure includes a substrate, a waveguide, doping regions, an optical attenuating member, and a dielectric layer. The waveguide is extended over the substrate. The doping regions are disposed over the substrate, and include a first doping region, a second doping region opposite to the first doping region and separated from the first doping region by the waveguide, a first electrode extended over the substrate and in the first doping region, and a second electrode extended over the substrate and in the second doping region. The first optical attenuating member is coupled with the waveguide and disposed between the waveguide and the first electrode. The dielectric layer is disposed over the substrate and covers the waveguide, the doping regions and the first optical attenuating member.Type: ApplicationFiled: March 29, 2023Publication date: October 3, 2024Inventors: HUAN-NENG CHEN, FENG-WEI KUO, MIN-HSIANG HSU, LAN-CHOU CHO, CHEWN-PU JOU, WEN-SHIANG LIAO
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Patent number: 12074125Abstract: A semiconductor package includes a first semiconductor device, a second semiconductor device vertically positioned above the first semiconductor device, and a ground shielded transmission path. The ground shielded transmission path couples the first semiconductor device to the second semiconductor device. The ground shielded transmission path includes a first signal path extending longitudinally between a first end and a second end. The first signal path includes a conductive material. A first insulating layer is disposed over the signal path longitudinally between the first end and the second end. The first insulating layer includes an electrically insulating material. A ground shielding layer is disposed over the insulating material longitudinally between the first end and the second end of the signal path. The ground shielding layer includes a conductive material coupled to ground.Type: GrantFiled: March 21, 2023Date of Patent: August 27, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Feng Wei Kuo, Wen-Shiang Liao, Chewn-Pu Jou, Huan-Neng Chen, Lan-Chou Cho, William Wu Shen
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Patent number: 12066658Abstract: An integrated optical device includes a substrate, a waveguide structure and a grating structure. The substrate has a waveguide region and a grating region adjacent to each other. The waveguide structure is disposed on the substrate in the waveguide region. The grating structure is disposed on the substrate in the grating region. In some embodiments, the grating structure includes grating bars and grating intervals arranged alternately, and widths of the grating bars of the grating structure are varied.Type: GrantFiled: April 21, 2022Date of Patent: August 20, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Feng-Wei Kuo, Wen-Shiang Liao
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Patent number: 12066662Abstract: Disclosed are apparatuses for optical coupling and a system for communication. In one embodiment, an apparatus for optical coupling including a substrate and a grating coupler is disclosed. The grating coupler is disposed on the substrate and includes a plurality of coupling gratings arranged along a first direction, wherein effective refractive indices of the plurality of coupling gratings gradually decrease along the first direction.Type: GrantFiled: June 14, 2023Date of Patent: August 20, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Feng-Wei Kuo, Wen-Shiang Liao, Robert Bogdan Staszewski, Jianglin Du
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Patent number: 12062629Abstract: Systems and methods are provided for an integrated chip. An integrated chip includes a package substrate including a plurality of first layers and a plurality of second layers, each second layer being disposed between a respective adjacent pair of the first layers. A transceiver unit is disposed above the package substrate. A waveguide unit including a plurality of waveguides having top and bottom walls formed in the first layers of the package substrate and sidewalls formed in the second layers of the package substrate.Type: GrantFiled: August 31, 2017Date of Patent: August 13, 2024Assignees: Taiwan Semiconductor Manufacturing Company Limited, The University of California, Los Angeles (UCLA)Inventors: Huan-Neng Chen, Chewn-Pu Jou, Feng Wei Kuo, Lan-Chou Cho, Wen-Shiang Liao, Yanghyo Kim
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Patent number: 12046544Abstract: A semiconductor device includes a method of manufacturing a semiconductor device. The method includes forming an interconnect structure. In some embodiments, the forming of the interconnect structure includes forming a first patterned layer over a substrate, attaching a die attach film (DAF) to a permalloy device and transporting the permalloy device to the first patterned layer through a pick and place operation, forming a second patterned layer in the same tier as the permalloy device, and bonding a semiconductor die to the interconnect structure. In some embodiments, the second patterned layer is aligned with the first patterned layer, forming a third patterned layer over the second patterned layer and the permalloy device. In some embodiments, the first patterned layer, the second patterned layer and the third patterned layer collectively form a coil winding around the permalloy device.Type: GrantFiled: July 29, 2022Date of Patent: July 23, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Ying-Chih Hsu, Wen-Shiang Liao
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Publication number: 20240243051Abstract: A package structure including a first radio frequency die, a second radio frequency die, an insulating encapsulant, a redistribution circuit structure, a first oscillation cavity and a second oscillation cavity is provided. A first frequency range of the first radio frequency die is different from a second frequency range of the second radio frequency die. The insulating encapsulant laterally encapsulates the first radio frequency die and the second radio frequency die. The redistribution circuit structure is disposed on the first radio frequency die, the second die and the insulating encapsulant. The first oscillation cavity is electrically connected to the first radio frequency die, and the second oscillation cavity is electrically connected to the second radio frequency die.Type: ApplicationFiled: March 29, 2024Publication date: July 18, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Wen-Shiang Liao
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Publication number: 20240232499Abstract: A method and system for generating a physical layout for a grating coupler integrated in a photonically-enabled circuit are disclosed herein. In some embodiments, the method receives a parametrized wavelength, a parametrized first refractive index, a parametrized second refractive index, a parametrized taper length, a parametrized width, a parametrized grating length, and a parametrized incident angle of the optical beam incident onto the grating coupler and generates a physical layout for the grating coupler based on the received parametrized inputs, the generating of the physical layout is according to a predefined model, and outputs the physical layout of the grating coupler for manufacturing under a semiconductor fabrication process.Type: ApplicationFiled: February 16, 2024Publication date: July 11, 2024Inventors: Feng-Wei KUO, Wen-Shiang LIAO
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Patent number: 12027478Abstract: A method of forming a semiconductor structure includes forming a first redistribution structure including a first conductive pattern. The method further includes placing a die over the first redistribution structure. The method further includes disposing a molding material over the first redistribution structure to surround the die. The method further includes removing a portion of the molding material to form an opening. The method further includes disposing a dielectric material into the opening to form a dielectric member. The method further includes forming a second redistribution structure over the molding material and the dielectric member, wherein the second redistribution structure includes an antenna structure over the dielectric member and electrically connected to the die.Type: GrantFiled: June 22, 2022Date of Patent: July 2, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Feng-Wei Kuo, Wen-Shiang Liao
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Publication number: 20240210617Abstract: A thermally tunable waveguide including an optical waveguide and a heater is provided. The optical waveguide includes a phase shifter. The heater is disposed over the optical waveguide. The heater includes a heating portion, pad portions and tapered portions. The heating portion overlaps with the phase shifter of the optical waveguide. The pad portions are disposed aside of the heating portion. Each of the pad portions is connected to the heating portion through one of the tapered portions respectively.Type: ApplicationFiled: March 7, 2024Publication date: June 27, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Feng-Wei KUO, Wen-Shiang Liao
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Publication number: 20240201439Abstract: A semiconductor package and a manufacturing method thereof are provided. A die stack in the semiconductor package includes a photonic die and an electronic die stacked on the photonic die by a face-to-face manner. A convex lens is disposed at a back surface of the electronic die, and is formed in an oval shape, such that optical beams can be collimated to have circular beam shape, as passing through the convex lens. In some embodiments, the semiconductor package includes more of the die stacks, and includes an interposer lying below the die stacks. In these embodiments, tilted reflectors are formed in the photonic dies and the interposer, to set up vertical optical paths between the interposer and the photonic dies, and lateral optical paths in the interposer. In this way, optical communication between the photonic dies can be established.Type: ApplicationFiled: February 8, 2023Publication date: June 20, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Feng-Wei KUO, Wen-Shiang Liao
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Publication number: 20240206193Abstract: A package structure and a formation method are provided. The method includes bonding a first memory-containing chip structure to a second memory-containing chip structure through dielectric-to-dielectric bonding and metal-to-metal bonding. The method also includes bonding a logic control chip structure to the second memory-containing chip structure through dielectric-to-dielectric bonding and metal-to-metal bonding. The logic control chip structure is formed using a more advanced technology node than the second memory-containing chip structure.Type: ApplicationFiled: January 9, 2023Publication date: June 20, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chuei-Tang WANG, Tso-Jung CHANG, Wen-Shiang LIAO, Jeng-Shien HSIEH, Chih-Peng LIN, Shih-Ping LIN, Chieh-Yen CHEN, Chen-Hua YU