Patents by Inventor Wen-Shun Lo
Wen-Shun Lo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240113091Abstract: The present disclosure provides a package with a semiconductor structure and a method for manufacturing the semiconductor structure. In some embodiments, a photonic semiconductor structure includes a substrate having a first side and a second side opposite to each other, a first redistribution layer disposed on the first side, an interconnect structure disposed on the second side of the substrate, a metal reflector disposed in the interconnect structure, a dielectric layer disposed over the interconnect structure, and a grating coupler disposed in the dielectric layer and overlapping the metal reflector.Type: ApplicationFiled: January 17, 2023Publication date: April 4, 2024Inventors: WEN-SHUN LO, JING-HWANG YANG, YINGKIT FELIX TSUI
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Publication number: 20230387241Abstract: A semiconductor device includes a substrate having a P-well region, an N-well region disposed on either side of and abutting the P-well region, and a deep N-well region disposed beneath and abutting both the P-well region and at least part of the N-well region on either side of the P-well region. The semiconductor device further includes a first conductive layer formed over a cathode region of the P-well region, where a Schottky barrier is formed at a junction of the first conductive layer and the P-well region. The semiconductor device further includes a second conductive layer formed over anode regions of the P-well region, where the anode regions are disposed on either side of the cathode region.Type: ApplicationFiled: May 26, 2022Publication date: November 30, 2023Inventors: Wen-Shun LO, Yu-Chi CHANG, Yingkit Felix TSUI
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Patent number: 11830888Abstract: In some embodiments, a photodetector is provided. The photodetector includes a first well having a first doping type disposed in a semiconductor substrate. A second well having a second doping type opposite the first doping type is disposed in the semiconductor substrate on a side of the first well. A first doped buried region having the second doping type is disposed in the semiconductor substrate, where the first doped buried region extends laterally through the semiconductor substrate beneath the first well and the second well. A second doped buried region having the second doping type is disposed in the semiconductor substrate and vertically between the first doped buried region and the first well, where the second doped buried region contacts the first well such that a photodetector p-n junction exists along the second doped buried region and the first well.Type: GrantFiled: May 19, 2021Date of Patent: November 28, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wen-Shun Lo, Felix Ying-Kit Tsui
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Publication number: 20230378203Abstract: In some embodiments, a photodetector is provided. The photodetector includes a first well having a first doping type disposed in a semiconductor substrate. A second well having a second doping type opposite the first doping type is disposed in the semiconductor substrate on a side of the first well. A first doped buried region having the second doping type is disposed in the semiconductor substrate, where the first doped buried region extends laterally through the semiconductor substrate beneath the first well and the second well. A second doped buried region having the second doping type is disposed in the semiconductor substrate and vertically between the first doped buried region and the first well, where the second doped buried region contacts the first well such that a photodetector p-n junction exists along the second doped buried region and the first well.Type: ApplicationFiled: August 7, 2023Publication date: November 23, 2023Inventors: Wen-Shun Lo, Felix Ying-Kit Tsui
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Publication number: 20230296928Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a semiconductor substrate, a first dielectric layer, a second dielectric layer, a light modulator, a heater, and a first conductive contact. The first dielectric layer is disposed on the semiconductor substrate. The second dielectric layer is disposed on the first dielectric layer. The light modulator is disposed in the first dielectric layer. The heater is disposed in the second dielectric layer and above the light modulator. The first conductive contact is electrically connected to the light modulator. A top surface of the heater is coplanar with a top surface of the first conductive contact.Type: ApplicationFiled: March 16, 2022Publication date: September 21, 2023Inventors: WEN-SHUN LO, YINGKIT FELIX TSUI
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Patent number: 11610907Abstract: A memory device includes a substrate, a first transistor, a second transistor, and a capacitor. The first transistor is over the substrate and includes a select gate. The second transistor is over the substrate and connected to the first transistor in series, in which the second transistor includes a floating gate. The capacitor is over the substrate and connected to the second transistor, wherein the capacitor includes a top electrode, a bottom electrode in the substrate, and an insulating layer between the top electrode and the bottom electrode. The insulating layer includes nitrogen. A nitrogen concentration of the insulating layer increases in a direction from the top electrode to the bottom electrode.Type: GrantFiled: May 27, 2021Date of Patent: March 21, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Wen-Shun Lo, Tai-Yi Wu, YingKit Felix Tsui
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Publication number: 20230033098Abstract: A memory device includes a substrate, a first transistor, a second transistor, and a capacitor. The first transistor is over the substrate and includes a select gate. The second transistor is over the substrate and connected to the first transistor in series, in which the second transistor includes a floating gate. The capacitor is over the substrate and connected to the second transistor, wherein the capacitor includes a top electrode, a bottom electrode in the substrate, and an insulating layer between the top electrode and the bottom electrode. The insulating layer includes nitrogen. A nitrogen concentration of the insulating layer increases in a direction from the top electrode to the bottom electrode.Type: ApplicationFiled: October 13, 2022Publication date: February 2, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Wen-Shun LO, Tai-Yi WU, YingKit Felix TSUI
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Publication number: 20220415914Abstract: In some embodiments, the present disclosure relates to an integrated chip (IC), including a substrate, a floating gate electrode disposed over the substrate, a contact etch stop layer (CESL) structure disposed over the floating gate electrode, an insulating stack separating the floating gate electrode from the CESL structure, the insulating stack including a first resist protective layer disposed over the floating gate electrode, a second resist protective layer disposed over the first resist protective layer, and an insulating layer separating the first resist protective layer from the second resist protective layer.Type: ApplicationFiled: August 23, 2021Publication date: December 29, 2022Inventors: Wen-Shun Lo, Tai-Yi Wu, Shih-Hsien Chen, Ying Kit Felix Tsui
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Publication number: 20220384465Abstract: A memory device includes a substrate, a first transistor, a second transistor, and a capacitor. The first transistor is over the substrate and includes a select gate. The second transistor is over the substrate and connected to the first transistor in series, in which the second transistor includes a floating gate. The capacitor is over the substrate and connected to the second transistor, wherein the capacitor includes a top electrode, a bottom electrode in the substrate, and an insulating layer between the top electrode and the bottom electrode. The insulating layer includes nitrogen. A nitrogen concentration of the insulating layer increases in a direction from the top electrode to the bottom electrode.Type: ApplicationFiled: May 27, 2021Publication date: December 1, 2022Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Wen-Shun LO, Tai-Yi WU, YingKit Felix Tsui
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Publication number: 20210272990Abstract: In some embodiments, a photodetector is provided. The photodetector includes a first well having a first doping type disposed in a semiconductor substrate. A second well having a second doping type opposite the first doping type is disposed in the semiconductor substrate on a side of the first well. A first doped buried region having the second doping type is disposed in the semiconductor substrate, where the first doped buried region extends laterally through the semiconductor substrate beneath the first well and the second well. A second doped buried region having the second doping type is disposed in the semiconductor substrate and vertically between the first doped buried region and the first well, where the second doped buried region contacts the first well such that a photodetector p-n junction exists along the second doped buried region and the first well.Type: ApplicationFiled: May 19, 2021Publication date: September 2, 2021Inventors: Wen-Shun Lo, Felix Ying-Kit Tsui
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Patent number: 11018168Abstract: In some embodiments, a photodetector is provided. The photodetector includes a first well having a first doping type disposed in a semiconductor substrate. A second well having a second doping type opposite the first doping type is disposed in the semiconductor substrate on a side of the first well. A first doped buried region having the second doping type is disposed in the semiconductor substrate, where the first doped buried region extends laterally through the semiconductor substrate beneath the first well and the second well. A second doped buried region having the second doping type is disposed in the semiconductor substrate and vertically between the first doped buried region and the first well, where the second doped buried region contacts the first well such that a photodetector p-n junction exists along the second doped buried region and the first well.Type: GrantFiled: May 10, 2019Date of Patent: May 25, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Wen-Shun Lo, Felix Ying-Kit Tsui
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Patent number: 10985240Abstract: A Schottky diode device includes a substrate having a first conductivity type, a first well region having a second conductivity type disposed in the substrate, and a first doped region having the second conductivity type in the first well region, wherein the first doped region includes a first portion and a second portion, and the first portion and the second portion have different doping concentrations. The first portion includes a region having at least four sides, from a top-view perspective, abutting the second portion.Type: GrantFiled: May 12, 2020Date of Patent: April 20, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Wen-Shun Lo, Yu-Chi Chang, Felix Ying-Kit Tsui
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Patent number: 10964586Abstract: A semiconductor structure includes a substrate having a first region and a second region defined thereon, a first isolation in the first region, a second isolation in the second region, and a region surrounding the first isolation in the substrate. The substrate includes a first material, and the region includes the first material and a second material. The first isolation has a first width, the second isolation has a second width, and the first width is greater than the second width. A bottom and sidewalls of the first isolation are in contact with the region, and a bottom and sidewalls of the second isolation are in contact with the substrate.Type: GrantFiled: December 20, 2019Date of Patent: March 30, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Wen-Shun Lo, Yu-Chi Chang, Felix Ying-Kit Tsui
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Publication number: 20200286987Abstract: A Schottky diode device includes a substrate having a first conductivity type, a first well region having a second conductivity type disposed in the substrate, and a first doped region having the second conductivity type in the first well region, wherein the first doped region includes a first portion and a second portion, and the first portion and the second portion have different doping concentrations. The first portion includes a region having at least four sides, from a top-view perspective, abutting the second portion.Type: ApplicationFiled: May 12, 2020Publication date: September 10, 2020Inventors: WEN-SHUN LO, YU-CHI CHANG, FELIX YING-KIT TSUI
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Patent number: 10763329Abstract: A semiconductor device includes a semiconductor substrate, a gate electrode, a channel region, a pair of source/drain regions and a threshold voltage adjusting region. The gate electrode is over the semiconductor substrate. The channel region is between the semiconductor substrate and the gate electrode. The channel region includes a pair of first sides opposing to each other in a channel length direction, and a pair of second sides opposing to each other in a channel width direction. The source/drain regions are adjacent to the pair of first sides of the channel region in the channel length direction. The threshold voltage adjusting region covers the pair of second sides of the channel region in the channel width direction, and exposing the pair of first sides of the channel region in the channel length direction.Type: GrantFiled: July 1, 2019Date of Patent: September 1, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Wen-Shun Lo, Yu-Chi Chang, Felix Ying-Kit Tsui
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Patent number: 10692788Abstract: A conductive-insulator-semiconductor (CIS) device with low flicker noise is provided. In some embodiments, the CIS device comprises a semiconductor substrate, a pair of source/drain regions, a selectively-conductive channel, and a gate electrode. The pair of source/drain regions is in the semiconductor substrate, and the source/drain regions are laterally spaced. The selectively-conductive channel is in the semiconductor substrate, and extends laterally in a first direction, from one of the source/drain regions to another one of the source/drain regions. The gate electrode comprises a pair of peripheral segments and a central segment. The peripheral segments extend laterally in parallel in the first direction. The central segment covers the selectively-conductive channel and extends laterally in a second direction transverse to the first direction, from one of the peripheral segments to another one of the peripheral segments. A method for manufacturing the CIS device is also provided.Type: GrantFiled: August 28, 2017Date of Patent: June 23, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Wen-Shun Lo, Ching-Hsien Huang, Yu-Chi Chang
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Patent number: 10665727Abstract: Present disclosure provides a semiconductor structure, including a semiconductor substrate having a top surface, a first well region of a first conductivity type in the semiconductor substrate, a second well region of a second conductivity type in the semiconductor substrate, laterally surrounding the first well region, and an isolation region in the first well region and the second well region in proximity to the top surface. The first well region includes a first lighter doped region in proximity to the top surface, and a heavier doped region under the first lighter doped region. Present disclosure also provides a method for manufacturing the semiconductor structure described herein.Type: GrantFiled: July 13, 2018Date of Patent: May 26, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Wen-Shun Lo, Felix Ying-Kit Tsui
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Patent number: 10658456Abstract: The present disclosure provides a method of manufacturing a Schottky diode. The method includes: providing a substrate; forming a first well region in the substrate; defining a first portion and a second portion on a surface of the first well region and performing a first ion implantation on the first portion while keeping the second portion from being implanted; forming a first doped region by heating the substrate to cause dopant diffusion between the first portion and the second portion; and forming a metal-containing layer on the first doped region to obtain a Schottky barrier interface.Type: GrantFiled: December 17, 2018Date of Patent: May 19, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Wen-Shun Lo, Yu-Chi Chang, Felix Ying-Kit Tsui
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Publication number: 20200135540Abstract: A semiconductor structure includes a substrate having a first region and a second region defined thereon, a first isolation in the first region, a second isolation in the second region, and a region surrounding the first isolation in the substrate. The substrate includes a first material, and the region includes the first material and a second material. The first isolation has a first width, the second isolation has a second width, and the first width is greater than the second width. A bottom and sidewalls of the first isolation are in contact with the region, and a bottom and sidewalls of the second isolation are in contact with the substrate.Type: ApplicationFiled: December 20, 2019Publication date: April 30, 2020Inventors: WEN-SHUN LO, YU-CHI CHANG, FELIX YING-KIT TSUI
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Publication number: 20200098803Abstract: In some embodiments, a photodetector is provided. The photodetector includes a first well having a first doping type disposed in a semiconductor substrate. A second well having a second doping type opposite the first doping type is disposed in the semiconductor substrate on a side of the first well. A first doped buried region having the second doping type is disposed in the semiconductor substrate, where the first doped buried region extends laterally through the semiconductor substrate beneath the first well and the second well. A second doped buried region having the second doping type is disposed in the semiconductor substrate and vertically between the first doped buried region and the first well, where the second doped buried region contacts the first well such that a photodetector p-n junction exists along the second doped buried region and the first well.Type: ApplicationFiled: May 10, 2019Publication date: March 26, 2020Inventors: Wen-Shun Lo, Felix Ying-Kit Tsui