Patents by Inventor Wen-Shun Lo

Wen-Shun Lo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6906377
    Abstract: A flash memory cell is described, including at least a substrate, a tunnel oxide layer, a floating gate, an insulating layer, a control gate and an inter-gate dielectric layer. The tunnel oxide layer is disposed on the substrate. The floating gate is disposed on the tunnel oxide layer, and is constituted by a first conductive layer on the tunnel oxide layer and a second conductive layer on the first conductive layer. The second conductive layer has a bottom lower than the top surface of the first conductive layer, and has a bowl-like cross section. The insulating layer is disposed between the floating gates, and each control gate is disposed on a floating gate with an inter-gate dielectric layer between them.
    Type: Grant
    Filed: May 30, 2003
    Date of Patent: June 14, 2005
    Assignee: Winbond Electronics Corp.
    Inventors: Chih-Jung Ni, Chung-Ming Chu, Tu-Hao Yu, Kuo-Chen Wang, Wen-Shun Lo, Haochieh Liu
  • Publication number: 20040191992
    Abstract: A flash memory cell is described, including at least a substrate, a tunnel oxide layer, a floating gate, an insulating layer, a control gate and an inter-gate dielectric layer. The tunnel oxide layer is disposed on the substrate. The floating gate is disposed on the tunnel oxide layer, and is constituted by a first conductive layer on the tunnel oxide layer and a second conductive layer on the first conductive layer. The second conductive layer has a bottom lower than the top surface of the first conductive layer, and has a bowl-like cross section. The insulating layer is disposed between the floating gates, and each control gate is disposed on a floating gate with an inter-gate dielectric layer between them.
    Type: Application
    Filed: May 30, 2003
    Publication date: September 30, 2004
    Inventors: Chih-Jung Ni, Chung-Ming Chu, Tu-Hao Yu, Kuo-Chen Wang, Wen-Shun Lo, Haochieh Liu
  • Publication number: 20040029389
    Abstract: A method for fabricating a shallow trench isolation structure with self-aligned floating gates is described. The method utilizes a sacrificial layer to form an isolation trench with ladder profile on a substrate. A tunnel oxide layer, a floating gate polysilicon layer and a patterned silicon nitride layer as a hard mask layer are sequentially formed on the substrate. The floating gate polysilicon layer is etched up to the tunnel oxide layer and the silicon nitride layer serves as a hard mask. The sacrificial layer is formed around the floating gate polysilicon layer in situ. After etching the substrate for forming the trench, the sacrificial layer is removed. Heating the trench forms a liner oxide layer and then depositing a silicon dioxide layer fills the trench. The method according to the invention reduces the voids in the trench and improves the yield of mass production.
    Type: Application
    Filed: August 6, 2002
    Publication date: February 12, 2004
    Applicant: WINBOND ELECTRONICS CORPORATION
    Inventor: Wen-Shun Lo