Abstract: Present disclosure provides a semiconductor structure, including a semiconductor substrate having a top surface, a first well region of a first conductivity type in the semiconductor substrate, a second well region of a second conductivity type in the semiconductor substrate, laterally surrounding the first well region, and an isolation region in the first well region and the second well region in proximity to the top surface. The first well region includes a first lighter doped region in proximity to the top surface, and a heavier doped region under the first lighter doped region. Present disclosure also provides a method for manufacturing the semiconductor structure described herein.

Abstract: A method for manufacturing a semiconductor structure including isolations includes receiving a substrate including a first region and a second region; forming a patterned hard mask, the patterned hard mask including a first opening exposing a portion of the first region and a second opening exposing a portion of the second region; removing portions of the substrate to form a first trench in the first region and to form a second trench in the second region; performing an ion implantation to a portion of the patterned hard mask in the first region and a portion of the substrate exposed from the first trench; enlarging the first opening to form a third opening over the first trench and enlarging the second opening to form a fourth opening over the second trench; and forming a first isolation by filling the first trench and a second isolation by filling the second trench.

Abstract: A semiconductor device includes a semiconductor substrate, a gate electrode, a channel region, a pair of source/drain regions and a threshold voltage adjusting region. The gate electrode is over the semiconductor substrate. The channel region is between the semiconductor substrate and the gate electrode. The channel region includes a pair of first sides opposing to each other in a channel length direction, and a pair of second sides opposing to each other in a channel width direction. The source/drain regions are adjacent to the pair of first sides of the channel region in the channel length direction. The threshold voltage adjusting region covers the pair of second sides of the channel region in the channel width direction, and exposing the pair of first sides of the channel region in the channel length direction.

Abstract: A semiconductor device includes a semiconductor substrate, a gate electrode, a pair of source/drain regions and a a threshold voltage adjusting region. The gate electrode is over the semiconductor substrate. The channel region is between the semiconductor substrate and the gate electrode. The source/drain regions are adjacent to two opposing sides of the channel region in a channel length direction. The threshold voltage adjusting region is adjacent to two opposing sides of the channel region in a channel width direction, wherein the threshold voltage adjusting region and the channel region have the same doping type.

Abstract: A method for manufacturing a semiconductor structure including isolations includes receiving a substrate including a first region and a second region; forming a patterned hard mask, the patterned hard mask including a first opening exposing a portion of the first region and a second opening exposing a portion of the second region; removing portions of the substrate to form a first trench in the first region and to form a second trench in the second region; performing an ion implantation to a portion of the patterned hard mask in the first region and a portion of the substrate exposed from the first trench; enlarging the first opening to form a third opening over the first trench and enlarging the second opening to form a fourth opening over the second trench; and forming a first isolation by filling the first trench and a second isolation by filling the second trench.

Abstract: The present disclosure provides a method of manufacturing a Schottky diode. The method includes: providing a substrate; forming a first well region in the substrate; defining a first portion and a second portion on a surface of the first well region and performing a first ion implantation on the first portion while keeping the second portion from being implanted; forming a first doped region by heating the substrate to cause dopant diffusion between the first portion and the second portion; and forming a metal-containing layer on the first doped region to obtain a Schottky barrier interface.

Abstract: A semiconductor device includes a semiconductor substrate, a gate electrode, a pair of source/drain regions and a a threshold voltage adjusting region. The gate electrode is over the semiconductor substrate. The channel region is between the semiconductor substrate and the gate electrode. The source/drain regions are adjacent to two opposing sides of the channel region in a channel length direction. The threshold voltage adjusting region is adjacent to two opposing sides of the channel region in a channel width direction, wherein the threshold voltage adjusting region and the channel region have the same doping type.

Abstract: A conductive-insulator-semiconductor (CIS) device with low flicker noise is provided. In some embodiments, the CIS device comprises a semiconductor substrate, a pair of source/drain regions, a selectively-conductive channel, and a gate electrode. The pair of source/drain regions is in the semiconductor substrate, and the source/drain regions are laterally spaced. The selectively-conductive channel is in the semiconductor substrate, and extends laterally in a first direction, from one of the source/drain regions to another one of the source/drain regions. The gate electrode comprises a pair of peripheral segments and a central segment. The peripheral segments extend laterally in parallel in the first direction. The central segment covers the selectively-conductive channel and extends laterally in a second direction transverse to the first direction, from one of the peripheral segments to another one of the peripheral segments. A method for manufacturing the CIS device is also provided.

Abstract: A method of forming a serpentine resistor includes: setting a total length of a schematic resistor to make the schematic resistor to have a first resistance according to a sheet resistance; forming, by using a processor, a serpentine layer corresponding to the schematic resistor, forming, by using the processor, a dummy layer over a portion of the serpentine layer to form a modified serpentine layer, measuring, by using the processor, a modified length of the modified serpentine layer, and comparing, by using the processor, the total length and the modified length to generate a comparison result.

Abstract: The present disclosure provides a method of manufacturing a Schottky diode. A substrate is provided. A first well region of a first conductive type is formed in the substrate. A first ion implantation of a second conductive type is performed on a first portion of the first well region while keeping a second portion of the first well region from being implanted. A first doped region is formed by heating the substrate to cause dopant diffusion between the first portion and the second portion. A metal-containing layer is formed on the first doped region to obtain a Schottky barrier interface.

Abstract: A semiconductor device includes a substrate, a buried doped layer, a first doped well, a multiplication region and a first contact doped region. The substrate has a first doping type, wherein the substrate includes a surface. The buried doped layer is in the substrate and exposed from the surface of the substrate, wherein the buried doped layer has a second doping type opposite to the first doping type. The first doped well is over the buried doped layer, wherein the first doped well has the first doping type. The multiplication region is proximal to an interface between the buried doped layer and the first doped well. The first contact doped region is over the first doped well, wherein the first contact doped region has the first doping type and a doped concentration higher than a doped concentration of the first doped well.

Abstract: A semiconductor device includes a substrate, a buried doped layer, a first doped well, a multiplication region and a first contact doped region. The substrate has a first doping type, wherein the substrate includes a surface. The buried doped layer is in the substrate and exposed from the surface of the substrate, wherein the buried doped layer has a second doping type opposite to the first doping type. The first doped well is over the buried doped layer, wherein the first doped well has the first doping type. The multiplication region is proximal to an interface between the buried doped layer and the first doped well. The first contact doped region is over the first doped well, wherein the first contact doped region has the first doping type and a doped concentration higher than a doped concentration of the first doped well.

Abstract: A method of forming a serpentine resistor includes: setting a total length of a schematic resistor to make the schematic resistor to have a first resistance according to a sheet resistance; forming, by using a processor, a serpentine layer corresponding to the schematic resistor, forming, by using the processor, a dummy layer over a portion of the serpentine layer to form a modified serpentine layer, measuring, by using the processor, a modified length of the modified serpentine layer, and comparing, by using the processor, the total length and the modified length to generate a comparison result.

Abstract: The invention provides a method for forming a via. A first dielectric layer is formed on a substrate. A conductive structure is formed in the first dielectric layer. A second dielectric layer is formed on the first dielectric layer and conductive structure. A first etching step is performed by using a first etching mixture to form a first via in the second dielectric layer. A second etching step is performed by using a second etching mixture to form a second via under the first via. The second via exposes at least a top surface of the conductive structure. An etching rate of the second etching step is slower than the first etching step.

Abstract: The invention provides a method for forming a via. A first dielectric layer is formed on a substrate. A conductive structure is formed in the first dielectric layer. A second dielectric layer is formed on the first dielectric layer and conductive structure. A first etching step is performed by using a first etching mixture to form a first via in the second dielectric layer. A second etching step is performed by using a second etching mixture to form a second via under the first via. The second via exposes at least a top surface of the conductive structure. An etching rate of the second etching step is slower than the first etching step.

Abstract: A method of manufacturing an opening is described. First, a substrate including a conductive portion and a dielectric layer both formed thereon is provided. The conductive portion at least includes a conductive layer and a passivation layer from bottom-up, and the dielectric layer covers the conductive portion. A first dry etching step is then performed to form an opening on the passivation layer by using a reactive gas containing a high polymer gas. The bottom of the opening has an initial dimension, and an obtuse angle is included by the bottom of the opening and an inner sidewall of the opening. Next, an opening enlarging step is performed to reach a target dimension of the bottom of the opening. The target dimension is larger than the initial dimension and to the least extent the conductive layer is not exposed by the opening.

Abstract: A method of forming a bonding pad opening is provided. A passivation layer and a mask layer are sequentially formed on a substrate having a bonding pad formed thereon. Thereafter, the passivation layer is etched to form an opening with use of an anti-reflection coating (ARC) layer of the bonding pad as an etching stop layer. Next, a dry removal process is performed to remove the mask layer. Afterwards, a wet cleaning process is performed to remove the residual mask layer or a polymer produced by previous manufacturing processes. Thereafter, the ARC layer is removed through performing an etching process with use of the passivation layer as a hard mask layer, so as to form the bonding pad opening.

Abstract: A method of forming a bonding pad opening is provided. A passivation layer and a mask layer are sequentially formed on a substrate having a bonding pad formed thereon. Thereafter, the passivation layer is etched to form an opening with use of an anti-reflection coating (ARC) layer of the bonding pad as an etching stop layer. Next, a dry removal process is performed to remove the mask layer. Afterwards, a wet cleaning process is performed to remove the residual mask layer or a polymer produced by previous manufacturing processes. Thereafter, the ARC layer is removed through performing an etching process with use of the passivation layer as a hard mask layer, so as to form the bonding pad opening.

Abstract: A method of manufacturing an opening is described. First, a substrate including a conductive portion and a dielectric layer both formed thereon is provided. The conductive portion at least includes a conductive layer and a passivation layer from bottom-up, and the dielectric layer covers the conductive portion. A first dry etching step is then performed to form an opening on the passivation layer by using a reactive gas containing a high polymer gas. The bottom of the opening has an initial dimension, and an obtuse angle is included by the bottom of the opening and an inner sidewall of the opening. Next, an opening enlarging step is performed to reach a target dimension of the bottom of the opening. The target dimension is larger than the initial dimension and to the least extent the conductive layer is not exposed by the opening.

Abstract: A method of manufacturing a gate dielectric layer is described. First, a substrate including a high voltage device region and a low voltage device region is provided. Plural isolation structures are formed in the substrate and protrude from the substrate. A high voltage gate dielectric layer is then formed on the substrate, and a passivation layer is formed on the high voltage gate dielectric layer in the high voltage device region. Next, a dry etching step is performed to remove a portion of the high voltage gate dielectric layer in the low voltage device region. Thereafter, a wet etching step is performed to remove the remaining high voltage gate dielectric layer in the low voltage device region. The passivation layer is then removed and a low voltage gate dielectric layer is formed on the substrate in the low voltage device region.