Patents by Inventor Wen Tsai

Wen Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240096701
    Abstract: A device includes: a stack of semiconductor nanostructures; a gate structure wrapping around the semiconductor nanostructures, the gate structure extending in a first direction; a source/drain region abutting the gate structure and the stack in a second direction transverse the first direction; a contact structure on the source/drain region; a backside conductive trace under the stack, the backside conductive trace extending in the second direction; a first through via that extends vertically from the contact structure to a top surface of the backside dielectric layer; and a gate isolation structure that abuts the first through via in the second direction.
    Type: Application
    Filed: May 17, 2023
    Publication date: March 21, 2024
    Inventors: Chun-Yuan CHEN, Huan-Chieh SU, Ching-Wei TSAI, Shang-Wen CHANG, Yi-Hsun CHIU, Chih-Hao WANG
  • Publication number: 20240096756
    Abstract: A method of making a semiconductor device includes manufacturing a first transistor over a first side of a substrate. The method further includes depositing a spacer material against a sidewall of the first transistor. The method further includes recessing the spacer material to expose a first portion of the sidewall of the first transistor. The method further includes manufacturing a first electrical connection to the transistor, a first portion of the electrical connection contacts a surface of the first transistor farthest from the substrate, and a second portion of the electrical connect contacts the first portion of the sidewall of the first transistor. The method further includes manufacturing a self-aligned interconnect structure (SIS) extending along the spacer material, wherein the spacer material separates a portion of the SIS from the first transistor, and the first electrical connection directly contacts the SIS.
    Type: Application
    Filed: November 22, 2023
    Publication date: March 21, 2024
    Inventors: Chih-Yu LAI, Chih-Liang CHEN, Chi-Yu LU, Shang-Syuan CIOU, Hui-Zhong ZHUANG, Ching-Wei TSAI, Shang-Wen CHANG
  • Publication number: 20240094783
    Abstract: An example computing device includes a first housing portion, a second housing portion moveably connected to the first housing portion, a link to selectively secure the second housing portion to the first housing portion to inhibit movement of the second housing portion relative to the first housing portion, and a shape-memory alloy element to release the link to allow the second housing portion to move relative to the first housing portion.
    Type: Application
    Filed: September 15, 2022
    Publication date: March 21, 2024
    Inventors: Yu-Wen LIN, Chia-Ming TSAI, Shih-Jen CHOU, John Joseph GRODEN
  • Publication number: 20240096805
    Abstract: In an embodiment, a method of forming a structure includes forming a first transistor and a second transistor over a first substrate; forming a front-side interconnect structure over the first transistor and the second transistor; etching at least a backside of the first substrate to expose the first transistor and the second transistor; forming a first backside via electrically connected to the first transistor; forming a second backside via electrically connected to the second transistor; depositing a dielectric layer over the first backside via and the second backside via; forming a first conductive line in the dielectric layer, the first conductive line being a power rail electrically connected to the first transistor through the first backside via; and forming a second conductive line in the dielectric layer, the second conductive line being a signal line electrically connected to the second transistor through the second backside via.
    Type: Application
    Filed: December 1, 2023
    Publication date: March 21, 2024
    Inventors: Shang-Wen Chang, Yi-Hsun Chiu, Cheng-Chi Chuang, Ching-Wei Tsai, Wei-Cheng Lin, Shih-Wei Peng, Jiann-Tyng Tzeng
  • Publication number: 20240097007
    Abstract: A semiconductor device is described. An isolation region is disposed on the substrate. A plurality of channels extend through the isolation region from the substrate. The channels including an active channel and an inactive channel. A dummy fin is disposed on the isolation region and between the active channel and the inactive channel. An active gate is disposed over the active channel and the inactive channel, and contacts the isolation region. A dielectric material extends through the active gate and contacts a top of the dummy fin. The inactive channel is a closest inactive channel to the dielectric material. A long axis of the active channel extends in a first direction. A long axis of the active gate extends in a second direction. The active channel extends in a third direction from the substrate. The dielectric material is closer to the inactive channel than to the active channel.
    Type: Application
    Filed: November 22, 2023
    Publication date: March 21, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Yao Lin, Hsiao Wen Lee, Ya-Yi Tsai, Shu-Uei Jang, Chih-Han Lin, Shu-Yuan Ku
  • Patent number: 11935957
    Abstract: Semiconductor device structures having gate structures with tunable threshold voltages are provided. Various geometries of device structure can be varied to tune the threshold voltages. In some examples, distances from tops of fins to tops of gate structures can be varied to tune threshold voltages. In some examples, distances from outermost sidewalls of gate structures to respective nearest sidewalls of nearest fins to the respective outermost sidewalls (which respective gate structure overlies the nearest fin) can be varied to tune threshold voltages.
    Type: Grant
    Filed: August 9, 2021
    Date of Patent: March 19, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Chiang Wu, Wei-Chin Lee, Shih-Hang Chiu, Chia-Ching Lee, Hsueh Wen Tsau, Cheng-Yen Tsai, Cheng-Lung Hung, Da-Yuan Lee, Ching-Hwanq Su
  • Patent number: 11934097
    Abstract: The present invention provides an imprinting method, which includes the steps of: adding a soluble material to a master mold; solidifying the soluble material to form a soluble mold having a mold pattern; adhering a taking device to the soluble mold to separate the soluble mold from the master mold; placing the soluble mold on a polymer layer of a workpiece for imprint; applying a high temperature and a pressure to the soluble mold to allow the polymer layer having an imprint pattern corresponding to the mold pattern and being solidified, and to remove the taking device from the soluble mold; and providing a solvent to dissolve the soluble mold to obtain an imprint workpiece having the imprint pattern.
    Type: Grant
    Filed: March 10, 2021
    Date of Patent: March 19, 2024
    Assignee: EVER RADIANT INCORPORATION
    Inventor: Sung-Wen Tsai
  • Patent number: 11934027
    Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.
    Type: Grant
    Filed: June 21, 2022
    Date of Patent: March 19, 2024
    Assignee: TDK TAIWAN CORP.
    Inventors: Chao-Chang Hu, Chih-Wei Weng, Chia-Che Wu, Chien-Yu Kao, Hsiao-Hsin Hu, He-Ling Chang, Chao-Hsi Wang, Chen-Hsien Fan, Che-Wei Chang, Mao-Gen Jian, Sung-Mao Tsai, Wei-Jhe Shen, Yung-Ping Yang, Sin-Hong Lin, Tzu-Yu Chang, Sin-Jhong Song, Shang-Yu Hsu, Meng-Ting Lin, Shih-Wei Hung, Yu-Huai Liao, Mao-Kuo Hsu, Hsueh-Ju Lu, Ching-Chieh Huang, Chih-Wen Chiang, Yu-Chiao Lo, Ying-Jen Wang, Shu-Shan Chen, Che-Hsiang Chiu
  • Publication number: 20240084017
    Abstract: Monoclonal antibodies against human Mac-1 are provided. These antibodies can bind to different states of Mac-1 so as to alter the biofunctions of Mac-1. These antibodies can modulate Th1/Th2 cytokine secretions by TLR-activated immune cells and can be used for the treatments of diseases related to acute and chronic inflammatory disorders, such as infectious diseases, and cancers.
    Type: Application
    Filed: December 30, 2021
    Publication date: March 14, 2024
    Applicant: Ascendo Biotechnology, Inc.
    Inventors: Yen-Ta Lu, Chia-Ming Chang, Ping-Yen Huang, I-Fang Tsai, Frank Wen-Chi Lee
  • Publication number: 20240085172
    Abstract: The device includes a projecting device, an image sensor and a computing circuit. The projecting device provides a light beam having a predetermined pattern that is projected onto an object. The image sensor receives the light beam reflected from the object to generate an image. The computing circuit compares the image with a first ground-truth image and a ground-truth image to generate a first depth value and a second depth value respectively. The first and second depth values are combined to generate a depth result.
    Type: Application
    Filed: September 11, 2022
    Publication date: March 14, 2024
    Inventors: Wu-Feng CHEN, Ching-Wen WANG, Cheng Che TSAI, Hsueh-Tsung LU
  • Patent number: 11924444
    Abstract: Method and apparatus for constrained de-blocking filter are disclosed. One method receives input data related to a current block in a current picture at a video encoder side or a video bitstream corresponding to compressed data including the current block in the current picture at a video decoder side, and determines a first boundary associated with the current block, wherein the first boundary corresponds to one vertical boundary or one horizontal boundary of the current block. The method then applies de-blocking process to a reconstructed current block corresponding to the current block to result in a filtered-reconstructed current block, using a plurality of first reference samples at a same side of the first boundary, and replaces a first set of the first reference samples by one or more padding values. The method then generates a filtered decoded picture including the filtered-reconstructed current block.
    Type: Grant
    Filed: April 11, 2022
    Date of Patent: March 5, 2024
    Assignee: HFI INNOVATION INC.
    Inventors: Chia-Ming Tsai, Chih-Wei Hsu, Ching-Yeh Chen, Tzu-Der Chuang, Yu-Wen Huang
  • Patent number: 11918329
    Abstract: A physiological detection device includes system including a first array PPG detector, a second array PPG detector, a display and a processing unit. The first array PPG detector is configured to generate a plurality of first PPG signals. The second array PPG detector is configured to generate a plurality of second PPG signals. The display is configured to show a detected result of the physiological detection system. The processing unit is configured to convert the plurality of first PPG signals and the plurality of second PPG signals to a first 3D energy distribution and a second 3D energy distribution, respectively, and control the display to show an alert message.
    Type: Grant
    Filed: April 23, 2021
    Date of Patent: March 5, 2024
    Assignee: PIXART IMAGING INC.
    Inventors: Chiung-Wen Lin, Wei-Ru Han, Yang-Ming Chou, Cheng-Nan Tsai, Ren-Hau Gu, Chih-Yuan Chuang
  • Publication number: 20240071909
    Abstract: A semiconductor package is provided. The semiconductor package includes an encapsulating layer, a semiconductor die formed in the encapsulating layer, and an interposer structure covering the encapsulating layer. The interposer structure includes an insulating base having a first surface facing the encapsulating layer, and a second surface opposite the first surface. The interposer structure also includes insulating features formed on the first surface of the insulating base and extending into the encapsulating layer. The insulating features is arranged in a matrix and faces a top surface of the semiconductor die. The interposer structure further includes first conductive features formed on the first surface of the insulating base and extending into the encapsulating layer. The first conductive features surround the matrix of the insulating features.
    Type: Application
    Filed: November 6, 2023
    Publication date: February 29, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Wen WU, Techi WONG, Po-Hao TSAI, Po-Yao CHUANG, Shih-Ting HUNG, Shin-Puu JENG
  • Publication number: 20240072816
    Abstract: A digital-to-analog converter and an operation method thereof are provided. The digital-to-analog converter includes a current source module, a decoder, a change indicator, and a random number generator. The decoder is coupled to the current source module and receives a digital input signal. The change indicator is coupled to the decoder and provides an indication signal to the decoder. The random number generator is coupled to the change indicator and provides a random number signal to the change indicator. The change indicator generates an indication signal according to the random number signal, and the decoder generates a control signal to the current source module according to the digital input signal and the indication signal, so that the current source module generates an analog output signal corresponding to the digital input signal according to the control signal.
    Type: Application
    Filed: November 21, 2022
    Publication date: February 29, 2024
    Applicants: Global Unichip Corporation, Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ting-Hao Wang, Hui-Wen Tsai, Shih-Chun Lo
  • Patent number: 11916091
    Abstract: A backside illumination (BSI) image sensor and a method of forming the same are provided. A device includes a substrate and a plurality of photosensitive regions in the substrate. The substrate has a first side and a second side opposite to the first side. The device further includes an interconnect structure on the first side of the substrate, and a plurality of recesses on the second side of the substrate. The plurality of recesses extend into a semiconductor material of the substrate.
    Type: Grant
    Filed: April 15, 2021
    Date of Patent: February 27, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Wen Hsu, Jiech-Fun Lu, Yeur-Luen Tu, U-Ting Chen, Shu-Ting Tsai, Hsiu-Yu Cheng
  • Patent number: 11915512
    Abstract: A three-dimensional sensing system includes a plurality of scanners each emitting a light signal to a scene to be sensed and receiving a reflected light signal, according to which depth information is obtained. Only one scanner executes transmitting corresponding light signal and receiving corresponding reflected light signal at a time.
    Type: Grant
    Filed: October 14, 2021
    Date of Patent: February 27, 2024
    Assignee: Himax Technologies Limited
    Inventors: Ching-Wen Wang, Cheng-Che Tsai, Ting-Sheng Hsu, Min-Chian Wu
  • Publication number: 20240024868
    Abstract: Provided is a microfluidic detection device, including a base with a microfluidic channel structure formed on the base and a lid covering the base. The microfluidic channel structure includes a sample well for loading a sample, a detection well having a first reagent for reacting with the sample, and a channel connecting the sample well and the detection well. The detection well has a recess deeper than the channel, and the base includes a protrusion corresponding to the recess to form a space between the protrusion and the recess. Also provided is a method for rapid diagnostic testing by the microfluidic detection device.
    Type: Application
    Filed: July 25, 2023
    Publication date: January 25, 2024
    Inventors: Ching-Yun Chen, Cherng-Jyh Ke, Shih-Tien Hsu, Ching-Wen Tsai, Si-Ting Wu, Yi-Hsuan Tung, Hsin-I Chiu, Sheng-Wen Chang, Jing-Ke Chen, Yueh-Teng Tsai, Ching Yu, Jian-Hua Chang
  • Publication number: 20230408704
    Abstract: A joint pilot detection method includes: obtaining a plurality of input signals that are derived from a plurality of satellite signals transmitted from a plurality of global navigation satellite system (GNSS) satellites, respectively, wherein each of the plurality of satellite signals carries a pilot component modulated by a secondary code; obtaining a plurality of code sequences that are replicas of secondary codes of the plurality of satellites, respectively; performing a plurality of correlation operations according to the plurality of input signals and the plurality of code sequences, for generating a plurality of correlation results, respectively; and performing pilot detection by jointly considering the plurality of correlation results.
    Type: Application
    Filed: June 12, 2023
    Publication date: December 21, 2023
    Applicant: MEDIATEK INC.
    Inventor: Han-Wen Tsai
  • Publication number: 20230394269
    Abstract: A card having a fingerprint sensor and a manufacturing method of the same are provided. The fingerprint sensor is disposed between a substrate and a protection layer. The protection layer has a first area and a second area thereon. The roughness of the second area is smaller than the roughness of the first area. The second area corresponds to the sensing area of the fingerprint sensor. When the user's finger is wet, the second area may effectively keep the water from remaining on it. Thus, the water does not affect the effect of fingerprint sensing.
    Type: Application
    Filed: May 22, 2023
    Publication date: December 7, 2023
    Applicant: ELAN MICROELECTRONICS CORPORATION
    Inventors: Yu-Kai LIN, Chien-Wen TSAI, Ta-Huang LIU
  • Patent number: 11836376
    Abstract: A convolution time de-interleaver includes an input buffer, an output buffer, a memory, an input control circuit, an output control circuit, and a controller. The memory includes a plurality of memory blocks. The input control circuit sequentially outputs a plurality of entries of data to a plurality of input register unit groups of the input buffer respectively and correspondingly. After a predetermined amount of data have been written to the input buffer, the controller writes part of data stored in the input buffer to a corresponding memory block. After the plurality of memory blocks are written, the controller writes data stored in a corresponding memory block to the output buffer. The output control circuit sequentially outputs a plurality of pieces of data stored in a plurality of output register unit groups of the output buffer.
    Type: Grant
    Filed: June 21, 2022
    Date of Patent: December 5, 2023
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Yi-Lin Shie, Wen-Tsai Liao, Lili Tan