Abstract: A system for analyzing vascular sound has a data acquiring module, a feature extraction module, and a feature analyzing module. The data acquiring module is used to acquire audio data from an individual. The feature extraction module is used to extract an audio feature from the audio data. The feature analyzing module is used to analyze the audio feature and to output an abnormality classification of a vascular sound corresponding to the audio data according to an analyze result of the audio feature.

Abstract: Provided is a system and method for prediction of obstructive coronary artery diseases, where a pre-processing module is configured to generate a left ventricular myocardium image from 3D images of a subject that is space-invariant, a flattening module is configured to resample the left ventricular myocardium image into flattened image in 3D spherical coordinate and preserve neighborhood relationship between myocardium of the subject, and a deep learning module is configured to predict probabilities of obstructive coronary artery disease in left anterior descending, left circumflex and right coronary artery and probability of patent coronary artery for calculation of compound probability of obstructive coronary artery disease for the subject.

Abstract: Packaged devices and methods of manufacturing the devices are described herein. The packaged devices may be fabricated using heterogeneous devices and asymmetric dual-side molding on a multi-layered redistribution layer (RDL) structure. The packaged devices may be formed with a heterogeneous three-dimensional (3D) Fan-Out System-in-Package (SiP) structure having small profiles and can be formed using a single carrier substrate.

Abstract: An electronic device includes a driving amplifier, a power amplifier, a power detector, and a bias circuit. The driving amplifier outputs a radio frequency (RF) signal. The power amplifier is electrically connected to the driving amplifier. The power amplifier includes an input end. The power amplifier receives the RF signal through the input end. The power amplifier amplifies the RF signal. The power detector is electrically coupled to the input end and detects the input power of the RF signal. The power detector outputs a driving voltage according to the input power. The bias circuit is electrically connected to the power amplifier and the power detector. The bias circuit outputs a first driving current to the power amplifier according to the driving voltage. The power amplifier amplifies the power of the RF signal from the input power to a target power according to the first driving current.

Abstract: One aspect of the present disclosure pertains to a semiconductor structure. The semiconductor structure includes first and second active regions extending lengthwise along a first direction and metal gate structures extending lengthwise along a second direction over channels of the first and second active regions. The semiconductor structure includes an insulating structure cutting through the metal gate structures. The insulating structure is disposed between the first and the second active regions along the second direction. The semiconductor structure includes source/drain (S/D) contacts over the insulating structure and over S/D features of the first and second active regions. The S/D contacts extend lengthwise along the second direction. And the semiconductor structure includes a feedthrough via contacting a bottom surface of the S/D contacts and penetrating through a portion of the insulating structure.

Abstract: The disclosure relates to methods for determining an endometrial status using a sample, for example, a blood plasma sample, from a subject, comprising: (a) performing an assay on the blood sample from the subject to determine a miRNA expression profile, wherein the miRNA expression profile comprises expression levels of a plurality of miRNA and (b) analyzing the miRNA expression profile to obtain a predictive score using a computer-based machine-learning model.

Abstract: A method for establishing a disease prediction model is provided. The method includes the steps of extracting feature values for multiple microbiota features from microbiota data of each of a plurality of samples, selecting a portion of the extracted microbiota features as selected features, and training a disease prediction model. Each piece of training data used in training the disease prediction model includes (i) disease data for each of the samples and (ii) the feature values of the selected features for the sample. The microbiota features include species-level features, microbiota interaction features, and community-level features.

Abstract: An interconnect fabrication method is disclosed herein that utilizes a disposable etch stop hard mask over a gate structure during source/drain contact formation and replaces the disposable etch stop hard mask with a dielectric feature (in some embodiments, dielectric layers having a lower dielectric constant than a dielectric constant of dielectric layers of the disposable etch stop hard mask) before gate contact formation. An exemplary device includes a contact etch stop layer (CESL) having a first sidewall CESL portion and a second sidewall CESL portion separated by a spacing and a dielectric feature disposed over a gate structure, where the dielectric feature and the gate structure fill the spacing between the first sidewall CESL portion and the second sidewall CESL portion. The dielectric feature includes a bulk dielectric over a dielectric liner. The dielectric liner separates the bulk dielectric from the gate structure and the CESL.

Abstract: A semiconductor device structure includes nanostructures formed over a substrate. The structure also includes a gate structure formed over and around the nanostructures. The structure also includes a spacer layer formed over a sidewall of the gate structure over the nanostructures. The structure also includes a source/drain epitaxial structure formed adjacent to the spacer layer. The structure also includes a contact structure formed over the source/drain epitaxial structure with an air spacer formed between the spacer layer and the contact structure.

Abstract: A light emitting diode includes a substrate and a semiconductor light emitting stack layer. The semiconductor light emitting stack layer is disposed on the substrate, and the substrate has four sidewalls, an upper surface, and a lower surface. At least one sidewall is provided with a first laser dotting region and a second laser dotting region. The first laser dotting region includes first laser dots, and the second laser dotting region includes second laser dots. A stress crack is present between the first laser dotting region and the second laser dotting region. A first distance D1 is present between the first laser dotting region and the stress crack, a second distance D2 is present between the second laser dotting region and the stress crack, and 0.7D2<D1<1.3D2.

Abstract: A semiconductor device includes a substrate including a well region of a first conductive type; a first gate electrode on the substrate; a second gate electrode on the substrate; a first doped region embedded within the well region and is of the first conductive type, a second doped region embedded within the well region and is of the first conductive type, and a third doped region embedded within the well region and is of the first conductive type; and a first interconnection structure electrically connecting the first gate electrode and the second gate electrode. The first doped region and the second doped region are on opposite sides of the first gate electrode.

Abstract: Provided is a package structure including a die; an electrically connecting structure having a die attach region and a peripheral region surrounding the die attach region, wherein the die is disposed on the electrically connecting structure within the die attach region; an insulating protrusion disposed in the peripheral region and extending in a thickness direction of the die; a conductive structure disposed on the electrically connecting structure and encapsulating the insulating protrusion, wherein the conductive structure is electrically coupled to the electrically connecting structure and the die; and a dielectric structure disposed on the electrically connecting structure and encapsulating the die and the conductive structure.

Abstract: A method of semiconductor fabrication includes providing a semiconductor structure having a substrate and first, second, third, and fourth fins above the substrate. The method further includes forming an n-type epitaxial source/drain (S/D) feature on the first and second fins, forming a p-type epitaxial S/D feature on the third and fourth fins, and performing a selective etch process on the semiconductor structure to remove upper portions of the n-type epitaxial S/D feature and the p-type epitaxial S/D feature such that more is removed from the n-type epitaxial S/D feature than the p-type epitaxial S/D feature.

Abstract: A semiconductor device includes a substrate; an interconnect structure over the substrate; a first passivation layer over the interconnect structure; a first conductive pad, a second conductive pad, and a conductive line disposed over the first passivation layer and electrically coupled to conductive features of the interconnect structure; a conformal second passivation layer over and extending along upper surfaces and sidewalls of the first conductive pad, the second conductive pad, and the conductive line; a first conductive bump and a second conductive bump over the first conductive pad and the second conductive pad, respectively, where the first conductive bump and the second conductive bump extend through the conformal second passivation layer and are electrically coupled to the first conductive pad and the second conductive pad, respectively; and a dummy bump over the conductive line, where the dummy bump is separated from the conductive line by the conformal second passivation layer.

Abstract: Systems for unlocking and locking a riser cage to a computing device are described herein. Such systems may include: a riser cage in a computing device; an axis member coupled to a first side of the riser cage and adapted to rotate about an axis; a handle coupled to the axis member and adapted to rotate the axis member about the axis; a cam, coupled to the axis member, and adapted to rotate about the axis when the axis member rotates; and a lever coupled to a second side of the riser cage and adapted to rotate about a pivot point when the cam rotates, wherein the lever engages with a stabilizing feature when the handle is in a first handle position.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a source/drain region formed in a semiconductor substrate, a source/drain contact structure formed over the source/drain region, and a silicide region formed between the source/drain region and the source/drain contact structure. The semiconductor device structure also includes a first insulating spacer surrounding and in direct contact with the source/drain contact structure and a second insulating spacer and a third insulating spacer respectively formed on two opposite sidewalls of the source/drain contact structure and in direct contact with an outer edge of the first insulating spacer. A first sidewall of the second insulating spacer and a second sidewall of the third insulating spacer are respectively aligned to two opposite side edges of the source/drain region.

Abstract: A pogo pin module and a control method of pogo pin temperature is provided. The pogo pin module includes a pogo pin assembly with a pogo pin, a sense control device, and a heating device. The sense control device is connected to the pogo pin and senses a pogo pin temperature. The heating device is connected to the sense control device. When the pogo pin temperature is less than a first temperature, the sense control device controls the heating device to heat the pogo pin such that the pogo pin temperature is greater than the first temperature to melt or evaporate a medium attached to the pogo pin. The pogo pin module and the control method of pogo pin temperature solves a problem that the conductivity of the pogo pin is worsened because the medium with the worse conductivity can be attached to the pogo pin.

Abstract: A synchronous backlight device and an operation method thereof are provided. The synchronous backlight device includes a pulse width modulation (PWM) control circuit and a backlight driving circuit. The PWM control circuit receives the video sync information from a video processing circuit and generates a PWM control signal. Wherein, the video sync information defines a plurality of video frame periods, the PWM control circuit at least divides each of the video frame periods into a first period and a second period, the lengths of the first periods of the video frame periods are equal to one another. The frequency of the PWM control signal in the first periods is different from the frequency of the PWM control signal in the second periods. The backlight driving circuit drives the backlight source of a display panel in accordance with the PWM control signal.