Patents by Inventor Wen-Yi Chen
Wen-Yi Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10298010Abstract: A method of protecting a serializer/deserializer (SERDES) differential input/output (I/O) circuit includes detecting an electrostatic discharge event. The method also includes selectively disengaging a power supply terminal from a pair of I/O transistors of the SERDES differential I/O circuit in response to the detected electrostatic discharge event. The method further includes selectively disengaging a ground terminal from the pair of I/O transistors of the SERDES differential I/O circuit in response to the detected electrostatic discharge event.Type: GrantFiled: March 31, 2016Date of Patent: May 21, 2019Assignee: QUALCOMM IncorporatedInventors: Eugene Robert Worley, Reza Jalilizeinali, Sreeker Dundigal, Wen-Yi Chen, Krishna Chaitanya Chillara, Taeghyun Kang
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Publication number: 20190015835Abstract: The present invention provides a portable thermal cycling device for quickly changing and regulating temperature, which is used for deoxyribonucleic acid (DNA) detection and amplification. The device adopts the concept of an electrical impedance method for detection, utilizes the spinning coating and electrospinning nanowires technologies to directly fabricate a thin film type thermal cycling device, and under the cooperation of a laser direct writing technology for patterning definition, enables the device to have the function of quickly raising/reducing temperature at one time for DNA amplification.Type: ApplicationFiled: August 4, 2017Publication date: January 17, 2019Inventors: TIEN-LI CHANG, HSIEH-CHEN HAN, ZHAO-CHI CHEN, WEN-YI CHEN
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Patent number: 9914395Abstract: An electrochromic rearview mirror contains a connection assembly, and the connection assembly includes: a first substrate, a first coating layer, a second coating layer, a packaging frame, an electrochromic layer, a first conductive glue, a second conductive glue, at least one third coating layer, at least one fourth coating layer, and a second substrate. The first substrate has a first face and a second face, and the second substrate has a third face and a fourth face. The second coating layer conducts electricity, each of the at least one fourth coating layer is fixed on the third face, and each of the at least one third coating layer is disposed on the third face. Furthermore, the packaging frame and the electrochromic layer are defined among the second coating layer, the fourth coating layer and the third coating layer.Type: GrantFiled: September 8, 2016Date of Patent: March 13, 2018Assignee: Licon Technologies Inc.Inventors: Wen-Li Chen, Wen-Yi Chen
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Publication number: 20180065557Abstract: An electrochromic rearview mirror contains a connection assembly, and the connection assembly includes: a first substrate, a first coating layer, a second coating layer, a packaging frame, an electrochromic layer, a first conductive glue, a second conductive glue, at least one third coating layer, at least one fourth coating layer, and a second substrate. The first substrate has a first face and a second face, and the second substrate has a third face and a fourth face. The second coating layer conducts electricity, each of the at least one fourth coating layer is fixed on the third face, and each of the at least one third coating layer is disposed on the third face. Furthermore, the packaging frame and the electrochromic layer are defined among the second coating layer, the fourth coating layer and the third coating layer.Type: ApplicationFiled: September 8, 2016Publication date: March 8, 2018Inventors: Wen-Li Chen, Wen-Yi Chen
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Publication number: 20170288398Abstract: A method of protecting a serializer/deserializer (SERDES) differential input/output (I/O) circuit includes detecting an electrostatic discharge event. The method also includes selectively disengaging a power supply terminal from a pair of I/O transistors of the SERDES differential I/O circuit in response to the detected electrostatic discharge event. The method further includes selectively disengaging a ground terminal from the pair of I/O transistors of the SERDES differential I/O circuit in response to the detected electrostatic discharge event.Type: ApplicationFiled: March 31, 2016Publication date: October 5, 2017Inventors: Eugene Robert WORLEY, Reza JALILIZEINALI, Sreeker DUNDIGAL, Wen-Yi CHEN, Krishna Chaitanya CHILLARA, Taeghyun KANG
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Patent number: 9543420Abstract: Protection device structures and related fabrication methods are provided. An exemplary semiconductor protection device includes a base region of semiconductor material having a first conductivity type, an emitter region within the base region having the opposite conductivity type, and a collector region of semiconductor material having the second conductivity type, wherein at least a portion of the base region resides between the emitter region and the collector region. A depth of the collector region is greater than a depth of the emitter region and less than or equal to a depth of the base region such that a distance between a lateral boundary of the emitter region and a proximal lateral boundary of the collector region is greater than zero and the collector region does not overlap or otherwise underlie the emitter region.Type: GrantFiled: July 19, 2013Date of Patent: January 10, 2017Assignee: NXP USA, Inc.Inventors: Wen-Yi Chen, Chai Ean Gill
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Patent number: 9502890Abstract: Protection device structures and related fabrication methods are provided. An exemplary semiconductor protection device includes a first base region of semiconductor material having a first conductivity type, a second base region of semiconductor material having the first conductivity type and a dopant concentration that is less than the first base region, a third base region of semiconductor material having the first conductivity type and a dopant concentration that is greater than the second base region, an emitter region of semiconductor material having a second conductivity type opposite the first conductivity type within the first base region, and a collector region of semiconductor material having the second conductivity type. At least a portion of the second base region resides between the third base region and the first base region and at least a portion of the first base region resides between the emitter region and the collector region.Type: GrantFiled: May 22, 2013Date of Patent: November 22, 2016Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Rouying Zhan, Chai Ean Gill, Wen-Yi Chen, Michael H. Kaneshiro
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Patent number: 9129806Abstract: Protection device structures and related fabrication methods are provided. An exemplary semiconductor protection device includes a base well region having a first conductivity type, an emitter region within the base well region having a second conductivity type opposite the first conductivity type, a collector region having the second conductivity type, a first floating region having the second conductivity type within the base well region between the emitter region and the collector region, and a second floating region having the first conductivity type within the base well region between the first floating region and the collector region. The floating regions within the base well region are electrically connected to reduce current gain and improve holding voltage.Type: GrantFiled: May 22, 2013Date of Patent: September 8, 2015Assignee: FREESCALE SEMICONDUCTOR INC.Inventors: Rouying Zhan, Chai Ean Gill, Wen-Yi Chen, Michael H. Kaneshiro
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Publication number: 20150249334Abstract: Techniques for reducing leakage current during normal operation of an electrostatic discharge (ESD) circuit are described herein. In one embodiment, a circuit comprises an internal circuit and an electrostatic discharge (ESD) rail clamp coupled in parallel to the internal circuit and between first and second power supply rails. The ESD rail clamp is operable to shunt ESD current from the first power supply rail to the second power supply rail via a low resistance shunt path. The ESD rail clamp comprises an ESD trigger circuit configured to detect an ESD event and a plurality of discharging transistors coupled in series. The ESD trigger circuit is configured to turn off the discharging transistors during normal operation and to turn on the discharging transistors to form the low resistance shunt path in response to detection of the ESD event.Type: ApplicationFiled: February 28, 2014Publication date: September 3, 2015Applicant: QUALCOMM INCORPORATEDInventors: Wen-Yi Chen, Sreeker Dundigal, Reza Jalilizeinali, Eugene Robert Worley
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Patent number: 9112351Abstract: An integrated circuit is provided. The integrated circuit may include, but is not limited to, a first node, a second node configured to be coupled to ground, an output driver, and a electrostatic discharge circuit electrically coupled to the first node, the second node, and the output driver. The electrostatic discharge circuit may include, but is not limited a high-pass filter configured to detect an electrostatic discharge event at the first node, a driving stage circuit electrically coupled to the high-pass filter and the output driver, the driving stage circuit configured to receive a signal from the high-pass filter when the high-pass filter detects the electrostatic discharge event and further configured to shunt an input of the output driver to the second node in response to the signal from the high-pass filter, and a step-down circuit electrically coupled to the driving stage circuit and configured to bias the driving stage circuit.Type: GrantFiled: February 5, 2013Date of Patent: August 18, 2015Assignee: FREESCALE SEMICONDUCTOR INC.Inventors: Wen-Yi Chen, Chai Ean Gill
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Patent number: 9054155Abstract: Die structures for electronic device packages and related fabrication methods are provided. An exemplary die structure includes a substrate having a first layer of semiconductor material including a semiconductor device formed thereon, a handle layer of semiconductor material, and a buried layer of dielectric material between the handle layer and the first layer. The die structure also includes a plurality of shunting regions in the first layer of semiconductor material, wherein each shunting region includes a doped region in the first layer that is electrically connected to the handle layer of semiconductor material, and a body region underlying the doped region that is contiguous with at least a portion of the first layer underlying a semiconductor device.Type: GrantFiled: March 7, 2013Date of Patent: June 9, 2015Assignee: FREESCALE SEMICONDUCTOR INC.Inventors: Chai Ean Gill, Wen-Yi Chen
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Publication number: 20150021739Abstract: Protection device structures and related fabrication methods are provided. An exemplary semiconductor protection device includes a base region of semiconductor material having a first conductivity type, an emitter region within the base region having the opposite conductivity type, and a collector region of semiconductor material having the second conductivity type, wherein at least a portion of the base region resides between the emitter region and the collector region. A depth of the collector region is greater than a depth of the emitter region and less than or equal to a depth of the base region such that a distance between a lateral boundary of the emitter region and a proximal lateral boundary of the collector region is greater than zero and the collector region does not overlap or otherwise underlie the emitter region.Type: ApplicationFiled: July 19, 2013Publication date: January 22, 2015Inventors: WEN-YI CHEN, CHAI EAN GILL
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Publication number: 20140346560Abstract: Protection device structures and related fabrication methods are provided. An exemplary semiconductor protection device includes a base well region having a first conductivity type, an emitter region within the base well region having a second conductivity type opposite the first conductivity type, a collector region having the second conductivity type, a first floating region having the second conductivity type within the base well region between the emitter region and the collector region, and a second floating region having the first conductivity type within the base well region between the first floating region and the collector region. The floating regions within the base well region are electrically connected to reduce current gain and improve holding voltage.Type: ApplicationFiled: May 22, 2013Publication date: November 27, 2014Inventors: Rouying ZHAN, Chai Ean GILL, Wen-Yi CHEN, Michael H. KANESHIRO
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Publication number: 20140347771Abstract: Protection device structures and related fabrication methods are provided. An exemplary semiconductor protection device includes a first base region of semiconductor material having a first conductivity type, a second base region of semiconductor material having the first conductivity type and a dopant concentration that is less than the first base region, a third base region of semiconductor material having the first conductivity type and a dopant concentration that is greater than the second base region, an emitter region of semiconductor material having a second conductivity type opposite the first conductivity type within the first base region, and a collector region of semiconductor material having the second conductivity type. At least a portion of the second base region resides between the third base region and the first base region and at least a portion of the first base region resides between the emitter region and the collector region.Type: ApplicationFiled: May 22, 2013Publication date: November 27, 2014Inventors: Rouying ZHAN, Chai Ean GILL, Wen-Yi CHEN, Michael H. KANESHIRO
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Publication number: 20140252552Abstract: Die structures for electronic device packages and related fabrication methods are provided. An exemplary die structure includes a substrate having a first layer of semiconductor material including a semiconductor device formed thereon, a handle layer of semiconductor material, and a buried layer of dielectric material between the handle layer and the first layer. The die structure also includes a plurality of shunting regions in the first layer of semiconductor material, wherein each shunting region includes a doped region in the first layer that is electrically connected to the handle layer of semiconductor material, and a body region underlying the doped region that is contiguous with at least a portion of the first layer underlying a semiconductor device.Type: ApplicationFiled: March 7, 2013Publication date: September 11, 2014Inventors: Chai Ean Gill, Wen-Yi Chen
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Publication number: 20140235465Abstract: A method of using Neutrilized DNA (N-DNA) as a surface probe for a high throughput detection platform is disclosed. FET and SPRi are used as high throughput detection platforms to demonstrate that the N-DNA surface probe produces good results and enhances detection sensitivity. The N-DNA modifies the charged oxygen ions (O?) on the phosphate backbone through methylation, ethylation, propylation, or alkylation, so that the backbone is not charged after this modification to increase the hybridization efficiency, sensitivity and to make the signal more clear.Type: ApplicationFiled: February 19, 2013Publication date: August 21, 2014Applicant: NATIONAL CENTRAL UNIVERSITYInventors: Wen-Yi Chen, Yun-Shyong Yang, Hardy Wai-Hong Chan
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Publication number: 20140218829Abstract: An integrated circuit is provided. The integrated circuit may include, but is not limited to, a first node, a second node configured to be coupled to ground, an output driver, and a electrostatic discharge circuit electrically coupled to the first node, the second node, and the output driver. The electrostatic discharge circuit may include, but is not limited a high-pass filter configured to detect an electrostatic discharge event at the first node, a driving stage circuit electrically coupled to the high-pass filter and the output driver, the driving stage circuit configured to receive a signal from the high-pass filter when the high-pass filter detects the electrostatic discharge event and further configured to shunt an input of the output driver to the second node in response to the signal from the high-pass filter, and a step-down circuit electrically coupled to the driving stage circuit and configured to bias the driving stage circuit.Type: ApplicationFiled: February 5, 2013Publication date: August 7, 2014Inventors: Wen-Yi Chen, Chai Ean Gill
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Publication number: 20140167705Abstract: A method of charging a battery includes following steps: First, a charging voltage is provided to charge the battery. Afterward, a charging control variable is judged whether to reach to an adjustment value. Afterward, the charging voltage is adjusted with a first voltage difference to continuously charge the battery when the charging control variable reaches to the adjustment value. Afterward, a health state value of the battery is judged whether less than or equal to a critical health state value. Finally, the charging voltage is increased with a second voltage difference to continuously charge the battery when the health state value of the battery is less than or equal to the critical health state value.Type: ApplicationFiled: December 19, 2012Publication date: June 19, 2014Applicant: Dynapack International Technology CorporationInventors: Ying-Yin CHANG, Chung-Hsing CHANG, Jiun-Ming CHEN, Yun-Chih LIN, Kun-Sheng SHEN, Wen-Yi CHEN
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Patent number: 8507946Abstract: An electrostatic discharge (ESD) protection device including a substrate, a first doped region, a second doped region, and a third doped region, a gate and a plurality of contacts is disclosed. The substrate includes a first conductive type. The first doped region is formed in the substrate and includes a second conductive type. The second doped region is formed in the substrate and includes the second conductive type. The third doped region is formed in the substrate, includes the first conductive type and is located between the first and the second doped regions. The gate is formed on the substrate, located between the first and the second doped regions and comprises a first through hole. The contacts pass through the first through hole to contact with the third doped region.Type: GrantFiled: March 4, 2011Date of Patent: August 13, 2013Assignees: Vanguard International Semiconductor Corporation, National Chiao Tung UniversityInventors: Yeh-Jen Huang, Yeh-Ning Jou, Ming-Dou Ker, Wen-Yi Chen, Chia-Wei Hung, Hwa-Chyi Chiou
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Patent number: 8281938Abstract: The invention discloses a nano-fiber material, wherein the nano-fiber material is formed by spinning an ionic polymer into a nano-fiber nonwoven, and the ionic polymer is represented by the formula: wherein: R1 includes phenyl sulfonate or alkyl sulfonate; R2 includes R3 includes and m/n is between 1/50 and 50/1, q?0.Type: GrantFiled: February 28, 2010Date of Patent: October 9, 2012Assignee: Industrial Technology Research InstituteInventors: Wen-Yi Chen, Shu-Hui Cheng, Feng-Hung Tseng