Abstract: Embodiments of the present disclosure provide methods and apparatuses for assigning network address prefix. A method performed by a control plane function may comprise: receiving, from a terminal device, a request for assigning a network address prefix; determining whether the network address prefix is assigned by the control plane function or a user plane function; transmitting, to the user plane function, a PFCP Session Modification Request for requesting the user plane function to assign the network address prefix, if it is determined that the network address prefix is assigned by the user plane function; receiving, from the user plane function, a PFCP Session Modification Response including an assigned network address prefix; and transmitting the assigned network address prefix to the terminal device. The specific procedure for the terminal device to obtain the network address prefix from a network entity not directly requested by the terminal device may be defined.

Abstract: A processing method for reducing warp of a nitrogen-doped wafer includes dividing a to-be-cut nitrogen-doped crystal ingot into a plurality of to-be-processed crystal ingot segments according to nitrogen content distribution, where each to-be-processed ingot segment corresponds to a nitrogen content range. The method further includes determining a processing condition corresponding to each to-be-processed crystal ingot segment according to correspondences between nitrogen content ranges and processing conditions, where the processing condition enables the corresponding to-be-processed crystal ingot segment to be prevented from warping during wire sawing; and performing cutting processing respectively on the each to-be-processed crystal ingot segment by using the processing condition corresponding to each to-be-processed crystal ingot segment, thereby obtaining a wafer by cutting the to-be-cut nitrogen-doped crystal ingot.

Abstract: Disclosed herein are related to a memory cell including one or more programmable resistors and a control transistor. In one aspect, a programmable resistor includes a gate structure and one or more source/drain structures for forming a transistor. A resistance of the programmable resistor may be set by applying a voltage to the gate structure, while the control transistor is enabled. Data stored by the programmable resistor can be read by sensing current through the programmable resistor, while the control transistor is disabled. In one aspect, the one or more programmable resistors and the control transistor are implemented by same type of components, allowing the memory cell to be formed in a compact manner through a simplified the fabrication process.

Abstract: A resistive memory device includes a bottom electrode, a top electrode and a resistance changing element. The top electrode is disposed above and spaced apart from the bottom electrode, and has a downward protrusion aligned with the bottom electrode. The resistance changing element covers side and bottom surfaces of the downward protrusion.

Abstract: The present invention relates to an early warning method before the occurrence of aflatoxin contamination.