Abstract: A device repairing method includes: collecting a device-parameter set of a target device; based on the device-parameter set, determining whether a to-be-repaired component exists among a plurality of device components of the target device, to obtain a determination result; in response to the determination result indicating that the to-be-repaired component exists, repairing the to-be-repaired component by operating a preset port in the to-be-repaired component, to obtain a repairment result; and according to the repairment result, determining whether the to-be-repaired component is repaired, and in response to the to-be-repaired component being not repaired, repeatedly executing the step of repairing the to-be-repaired component by operating the preset port in the to-be-repaired component, till the repairment result indicates that the to-be-repaired component is repaired or a repairment time quantity reaches a preset time-quantity threshold.

Abstract: An apparatus for non-contact current and voltage composite measurement includes: a current signal detection device, a voltage signal detection device, a zero-crossing detection circuit, and a control unit. The current signal detection device generates a current-induced electromotive force based on current flowing on the transmission line to be measured when there is current-voltage passing through the transmission line to be measured; the voltage signal detection device generates a voltage-induced electromotive force based on voltage flowing on the transmission line to be measured when there is current-voltage passing through the transmission line to be measured. The zero-crossing detection circuit performs zero-crossing detection on the current-induced electromotive force and the voltage-induced electromotive force to determine the phase difference between them.

Abstract: A CT energy extraction device is provided. A first accommodation cavity is provided in a first housing, and a second accommodation cavity is provided in a second housing. The first housing can be connected and joined with the second housing to form a ring shape, which is used to be placed on outside of a high-voltage line. A first iron core is disposed in the first accommodation cavity, and an energy-extraction coil is wound around the first iron core. A cable outlet is provided on the first housing, and the energy-extraction coil has pins extending from the cable outlet. A second iron core is disposed in the second accommodation cavity. When the first housing and the second housing are connected and joined, the first and second iron cores are joined to form a closed ring structure. An inflating assembly is provided on the first housing and/or the second housing.

Abstract: The present invention relates to novel compounds which are capable of inhibiting certain amine oxidase enzymes. These compounds are useful for treatment of a variety of indications, e.g., fibrosis, cancer and/or angiogenesis in human subjects as well as in pets and livestock. In addition, the present invention relates to pharmaceutical compositions containing these compounds, as well as various uses thereof.

Abstract: The present disclosure discloses a question analysis method, a device, a knowledge base question answering system and an electronic equipment. The method includes: analyzing a question to obtain N linearized sequences, N being an integer greater than 1; converting the N linearized sequences into N network topology maps; separately calculating a semantic matching degree of each of the N network topology maps to the question; and selecting a network topology map having a highest semantic matching degree to the question as a query graph of the question from the N network topology maps. According to the technology of the present disclosure, the query graph of the question can be obtained more accurately, and the accuracy of the question to the query graph is improved, thereby improving the accuracy of question analysis.

Abstract: Semiconductor structures, fabrication methods thereof, and memory systems are provided. In one aspect, a method of forming a semiconductor structure includes: forming a plurality of first trenches in a semiconductor base from a surface of the semiconductor base, forming a plurality of gate structures in the plurality of first trenches, forming a plurality of second trenches in the semiconductor base, and forming a plurality of isolation structures in the plurality of second trenches. The plurality of first trenches extend along a first direction. Each of the plurality of second trenches is between two adjacent trenches of the plurality of first trenches, and the plurality of second trenches extend along the first direction.

Abstract: Disclosed are a dynamic disturbance-induced rock burst test device and a test method. The test device comprise a supporting platform, a plurality of loading plates, an electromagnetic pulse emitting system, an acoustic emission monitoring system, a high-speed camera, an electromagnetic radiation detecting system and a confining pressure servo control loading system. The plurality of loading plates are arranged on a side wall of a coal rock sample and are placed inside a square chest, the electromagnetic pulse emitting system and the confining pressure servo control loading system are arranged inside a bar system, and an acoustic emission probe is arranged inside the loading plate. A three-dimensional real stress environment of the coal rock is simulated by simulating a shear stress through friction between the loading plate and the sample, as well as dynamic and static combined loading of multi-axial and multi-directional static confining pressure and stress wave disturbance.

Abstract: A container includes a tank body and a cover. The tank body defines an opening. The cover detachably covers the opening of the tank body. A sidewall of the tank body defines an accommodating groove. The cover includes a cover body and a plug-in piece extending from the cover body to the tank body. The plug-in piece is capable of extending into the accommodating groove. The container further includes a fixing piece, and the fixing piece detachably covers an opening of the accommodating groove and is capable of being buckled with the plug-in piece accommodated in the accommodating groove.

Abstract: The present invention relates to novel compounds which are capable of inhibiting certain amine oxidase enzymes. These compounds are useful for treatment of a variety of indications, e.g., fibrosis, cancer and/or angiogenesis in human subjects as well as in pets and livestock. In addition, the present invention relates to pharmaceutical compositions containing these compounds, as well as various uses thereof.

Abstract: A semiconductor structure includes a stack structure including interleaved conductive layers and dielectric layers, memory strings and slit structures extending through the stack structure, and top select gate cuts extending through the stack structure. At least two of the top select gate cuts are disposed between adjacent slit structures. One of the memory strings includes a memory film and a channel layer. The memory film includes a tunneling layer, a storage layer, and a blocking layer. Each of the top select gate cuts has a width smaller than a diameter of the memory strings.

Abstract: Provided is an information backhaul method, which is applied to a networking unit in a network system. The network system includes multiple stages of networking units that are cascaded, and each of the multiple stages of networking units includes multiple optical ports. The information backhaul method includes: acquiring cascade information of a networking unit in a current stage, where the cascade information of the networking unit in the current stage includes optical port information and identification information of the networking unit in the current stage; and feeding back the cascade information of the networking unit in the current stage. Further provided are a data allocation method, a networking unit, a data allocation controller, a network system and a computer-readable storage medium.

Abstract: A method for forming a 3D memory device is disclosed. The method includes forming an alternating dielectric stack on a substrate. Then a plurality of channel structures and dummy channel structures vertically penetrating the alternating dielectric stack are formed, The channel structures are located in a core region, and the dummy channel structures are located in a staircase region. A gate line silt structure is formed vertically penetrating the alternating dielectric stack and laterally extending in a first direction. The gate line silt structure includes a narrow portion that has a reduced width along a second direction different from the first direction.

Abstract: Embodiments of a three-dimensional (3D) memory device and fabrication methods are disclosed. In some embodiments, the method for forming the 3D memory device includes forming an alternating dielectric stack on a substrate, and forming channel holes that penetrate the alternating dielectric stack and expose at least a portion of the substrate. The method further includes forming top select gate openings that penetrate vertically an upper portion of the alternating dielectric stack and extend laterally. The method also includes forming slit openings parallel to the top select gate openings, wherein the slit openings penetrate vertically the alternating dielectric stack. The method also includes replacing the alternating dielectric stack with a film stack of alternating conductive and dielectric layers, forming top select gate cuts in the top select gate openings, and forming slit structures in the slit openings.

Abstract: Embodiments of three-dimensional (3D) memory devices and fabricating methods thereof are disclosed. The method includes: forming an alternating dielectric stack on a substrate; forming a structure strengthen plug in an upper portion of the alternating dielectric stack, wherein the structure strengthen plug has a narrow support body and two enlarged connecting portions; forming a gate line silt in the alternating dielectric stack to expose a sidewall of one enlarged connecting portion of the structure strengthen plug; and forming a gate line slit structure in the gate line slit including an enlarged end portion connected to the one enlarged connecting portion of the structure strengthen plug.

Abstract: In certain aspects, a three-dimensional (3D) memory device includes a semiconductor layer; a stack structure on the semiconductor layer, one or more stop structures, and second dielectric layers. The stack structure includes alternating conductive layers and first dielectric layers and has a core region and a staircase region adjacent to the core region. The one or more stop structures are in contact with the corresponding conductive layers and extend through the staircase region of the stack structure in a first direction toward the semiconductor layer. Each of the second dielectric layers is between two of the first dielectric layers. Each of the one or more stop structures is between one of the second dielectric layers and one of the conductive layers.

Abstract: 3D memory devices are disclosed. In an implementation, a 3D memory device includes a stack structure having a core area and a staircase area. The core area includes conductive layers interleaved with first dielectric layers. Each stair of the staircase area has a different number of conductive layers interleaved with a different number of first dielectric layers. The staircase area has contact structures that penetrate through the first surface, a respective one of the stairs, and dielectric material. Each of the contact structures is electrically connected to a contacting conductive layer of the different number of conductive layers of one of the stairs. The staircase area has second dielectric layers, each of which isolates a remainder of the different number of conductive layers of the respective one of the stairs other than the contacting conductive layer from a respective contact structure.

Abstract: A semiconductor device includes a base and a stack structure. The base includes a first surface defining at least one memory plane region. The stack structure is disposed on the first surface, and includes a first portion located at the edge of the memory plane region and a second portion different from the first portion. The first portion includes first contact structures penetrating through the stack structure in a first direction and extending to the base. The second portion includes second contact structures electrically connected with corresponding gate conductor layers in the stack structure. A top surface of the first contact structure away from the base is flush with a top surface of the second contact structure away from the base.

Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In one example, a 3D memory device includes a multi-layer stacked structure, where the multi-layer stacked structure includes a plurality of alternately stacked conductive layers and dielectric layers. The 3D memory device further includes a semiconductor layer over the multi-layer stacked structure, and a plurality of channel structures penetrating into the multi-layer stacked structure and the semiconductor layer. A first end of each channel structure is located within the semiconductor layer, and the first ends of the channel structures are aligned with one another.

Abstract: Embodiments of structure and methods for forming a three-dimensional (3D) memory device are provided. In an example, a 3D memory device includes a stack structure including a memory block including a plurality of memory cells. The 3D memory device also includes a first top select structure and a bottom select structure in the memory block and aligned with each other vertically; and a second top select structure in the memory block is separated from the first top select structure by at least one of the plurality of memory cells. The first top select structure, the bottom select structure, and the second top select structure each includes an insulating material.

Abstract: A semiconductor device includes a plurality of memory blocks. Each memory block includes a memory deck including interleaved first conductor layers and first dielectric layers, and a separation structure extending to separate two adjacent memory blocks. Each separation structure includes a dielectric stack including interleaved third dielectric layers and fourth dielectric layers. The third dielectric layers are in contact with the first dielectric layers, and the fourth dielectric layers are in contact with the first conductor layers.