Abstract: Embodiments of a three-dimensional (3D) memory device and fabrication methods are disclosed. In some embodiments, the method for forming the 3D memory device includes forming an alternating dielectric stack on a substrate, and forming channel holes that penetrate the alternating dielectric stack and expose at least a portion of the substrate. The method further includes forming top select gate openings that penetrate vertically an upper portion of the alternating dielectric stack and extend laterally. The method also includes forming slit openings parallel to the top select gate openings, wherein the slit openings penetrate vertically the alternating dielectric stack. The method also includes replacing the alternating dielectric stack with a film stack of alternating conductive and dielectric layers, forming top select gate cuts in the top select gate openings, and forming slit structures in the slit openings.

Abstract: Embodiments of structure and methods for forming a three-dimensional (3D) memory device are provided. In an example, a 3D memory device includes a memory stack, a plurality of channel structures, and a source structure. The memory stack is over a substrate and includes interleaved a plurality of conductor layers and a plurality of insulating layers. The plurality of channel structures extend vertically in the memory stack. The source structure extend in the memory stack. The source structure includes a plurality of source contacts each in a respective insulating structure, and two adjacent ones of the plurality of source contacts are conductively connected to one another.

Abstract: Embodiments of structure and methods for forming a three-dimensional (3D) memory device are provided. In an example, a 3D memory device includes a memory stack, a plurality of channel structures, and a source structure. The memory stack is over a substrate and includes interleaved a plurality of conductor layers and a plurality of insulating layers. The source structure includes a plurality of source contacts, and two adjacent ones of the plurality of source contacts are conductively connected to one another by a connection layer. A pair of first portions of the connection layer are over the two adjacent ones of the plurality of source contacts and a second portion of the connection layer being between the two adjacent ones of the plurality of source contacts. Top surfaces of the pair of first portions of the connection are coplanar with a top surface of the second portion.

Abstract: Embodiments of structure and methods for forming a three-dimensional (3D) memory device are provided. In an example, a 3D memory device includes a memory stack over a substrate, a plurality of channel structures, and a source structure. The memory stack includes interleaved a plurality of conductor layers and a plurality of insulating layers. The plurality of channel structures extend vertically in the memory stack. The source structure extend in the memory stack. The source structure includes a plurality of source contacts each in a respective insulating structure. At least two of the plurality of source contacts are in contact with and conductively connected to one another.

Abstract: Embodiments of structure and methods for forming a three-dimensional (3D) memory device are provided. In an example, a 3D memory device includes a stack structure and at least one source structure extending vertically and laterally and dividing the stack structure into a plurality of block regions. The stack structure may include a plurality of conductor layers and a plurality of insulating layers interleaved over a substrate. The at least one source structure includes at least one support structure extending along the vertical direction to the substrate, the at least one support structure being in contact with at least a sidewall of the respective source structure.

Abstract: Embodiments of structure and methods for forming a three-dimensional (3D) memory device are provided. In an example, the 3D memory device includes a memory stack having interleaved a plurality of conductor layers and a plurality of insulating layers extending laterally in the memory stack. The 3D memory device also includes a plurality of channel structures extending vertically through the memory stack into the substrate. The 3D memory device further includes at least one slit structure extending vertically and laterally in the memory stack and dividing a plurality of memory cells into at least one memory block, the at least one slit structure each including a plurality of slit openings and a support structure between adjacent slit openings. The support structure may be in contact with adjacent memory blocks and contacting the substrate.

Abstract: Embodiments of structure and methods for forming a three-dimensional (3D) memory device are provided. In an example, a 3D memory device includes a memory stack, a plurality of channel structures, a slit structure, and a source structure. The memory stack may be over a substrate and may include interleaved a plurality of conductor layers and a plurality of insulating layers extending laterally in the memory stack. The plurality of channel structures may extend vertically through the memory stack into the substrate. The slit structure may extend vertically and laterally in the memory stack and divide the plurality of memory cells into at least one memory block. The slit structure may include a plurality of protruding portions and a plurality of recessed portions arranged vertically along a sidewall of the slit structure.

Abstract: Embodiments of structure and methods for forming a three-dimensional (3D) memory device are provided. In an example, the 3D memory device includes a stack structure. The stack structure includes a plurality of conductor layers and a plurality of insulating layers interleaved over a substrate. The plurality of conductor layers include a pair of top select conductor layers divided by a first top select structure and a pair of bottom select conductor layers divided by a bottom select structure. The first top select structure and the bottom select structure extend along a horizontal direction and are aligned along a vertical direction. A plurality of channel structures extend along a vertical direction and into the substrate and are distributed on both sides of the top select structure and the bottom select structure.

Abstract: Embodiments of a semiconductor memory device include a substrate having a first region with peripheral devices, a second region with one or more memory arrays, and a third region between the first and the second regions. The semiconductor memory device also includes a protective structure for peripheral devices. The protective structure for peripheral devices of the semiconductor memory device includes a first dielectric layer and a barrier layer disposed on the first dielectric layer. The protective structure for peripheral devices of the semiconductor memory device further includes a dielectric spacer formed on a sidewall of the barrier layer and a sidewall of the first dielectric layer, wherein the protective structure is disposed over the first region and at least a portion of the third region.

Abstract: The present invention relates to novel compounds which are capable of inhibiting certain amine oxidase enzymes. These compounds are useful for treatment of a variety of indications, e.g., fibrosis, cancer and/or angiogenesis in human subjects as well as in pets and livestock. In addition, the present invention relates to pharmaceutical compositions containing these compounds, as well as various uses thereof.

Abstract: A non-transitory computer-readable storage medium includes instructions for commissioning a power meter that has a Bluetooth Low Energy (BLE) communication capability, the instructions, when executed by one or more processors of a mobile device, cause the mobile device to discover the presence of the power meter by recognizing a signal produced by the Bluetooth Low Energy (BLE) communication capability of the power meter and receive a unique identifier for the power meter. When the received unique identifier matches a unique identifier stored by the power meter, the mobile device will establish a communication link between the mobile device and the power meter using the Bluetooth Low Energy (BLE) communication capability of the power meter and will transmit one or more commissioning parameters to the power meter via the established communication link between the mobile device and the power meter.

Abstract: A power meter includes a plurality of terminals for receiving a measure of power consumption of each of one or more phases of power that is delivered to a load and a controller that is operatively coupled to the plurality of terminals. The controller is configured to determine a number of power monitor parameters based on the measure of power consumption of each of one or more phases of power that is delivered to the load. The controller is further configured to operate an interactive menu. The power meter includes a user interface that is configured to display the number of power monitor parameters based on the measure of power consumption of each of one or more phases of power that is delivered to the load and to enable a user to navigate the interactive menu using via one or more screens displayed on the user interface.

Abstract: A three-dimensional (3D) memory structure and a manufacturing method thereof are provided. The method includes the following steps. A 3D memory unit is formed on a first region of a substrate. A first insulation layer is formed on the first region and a second region of the substrate. A first planarization process is performed to the first insulation layer. The top surface of the first insulation layer on the first region and the top surface of the first insulation layer on the second region are coplanar after the first planarization process. A peripheral circuit is formed on the second region after the first planarization process. The influence of the process for forming the 3D memory unit on the peripheral circuit may be avoided. The manufacturing yield, the electrical performance, and the reliability of the 3D memory structure may be enhanced accordingly.

Abstract: Embodiments of a semiconductor memory device include a substrate having a first region with peripheral devices, a second region with one or more memory arrays, and a third region between the first and the second regions. The semiconductor memory device also includes a protective structure for peripheral devices. The protective structure for peripheral devices of the semiconductor memory device includes a first dielectric layer and a barrier layer disposed on the first dielectric layer. The protective structure for peripheral devices of the semiconductor memory device further includes a dielectric spacer formed on a sidewall of the barrier layer and a sidewall of the first dielectric layer, wherein the protective structure is disposed over the first region and at least a portion of the third region.

Abstract: The present invention relates to novel compounds which are capable of inhibiting certain amine oxidase enzymes. These compounds are useful for treatment of a variety of indications, e.g., fibrosis, cancer and/or angiogenesis in human subjects as well as in pets and livestock. In addition, the present invention relates to pharmaceutical compositions containing these compounds, as well as various uses thereof.

Abstract: The present invention relates to novel compounds which are capable of inhibiting certain amine oxidase enzymes. These compounds are useful for treatment of a variety of indications, e.g., fibrosis, cancer and/or angiogenesis in human subjects as well as in pets and livestock. In addition, the present invention relates to pharmaceutical compositions containing these compounds, as well as various uses thereof.

Abstract: A method of extruding a material, comprising providing the material into an extrusion chamber of an extrusion apparatus, wherein the extrusion chamber comprises an extrusion orifice and the extrusion apparatus comprises a first compression element and a second compression element in communication with the interior of the extrusion chamber, the first and second compression elements being independently movable relative to the extrusion chamber, moving at least one of the first and second compression elements to compress the material within the extrusion chamber and cause a velocity gradient in the extrusion material across the extrusion orifice and extruding the material through the extrusion orifice such that the velocity gradient forms an extrudate with a curved profile.

Abstract: The present invention provides a high-resolution Micro-OLED display module and a manufacturing method thereof. The method for manufacturing the high-resolution Micro-OLED comprises: S1, providing a substrate, and manufacturing light-emitting pixel units on the substrate; S2, encapsulating the light-emitting pixel units by a film encapsulation technique, and forming a film encapsulation layer; S3, manufacturing sub-pixel units on the surface of the film encapsulation layer, and depositing a metal reflective layer between two sub-pixel units which are adjacent to each other; S4, manufacturing a metal oxide layer on the surfaces of the metal reflective layer and the sub-pixel units by a deposition technique, to obtain a high-resolution Micro-OLED matrix; and S5, using a cover plate to encapsulate the high-resolution Micro-OLED matrix produced in step S4, to finish the manufacturing of a high-resolution Micro-OLED.

Abstract: The present invention relates to novel compounds which are capable of inhibiting certain amine oxidase enzymes. These compounds are useful for treatment of a variety of indications, e.g., fibrosis, cancer and/or angiogenesis in human subjects as well as in pets and livestock. In addition, the present invention relates to pharmaceutical compositions containing these compounds, as well as various uses thereof.