Abstract: The present invention relates to novel compounds which are capable of inhibiting certain amine oxidase enzymes. These compounds are useful for treatment of a variety of indications, e.g., fibrosis, cancer and/or angiogenesis in human subjects as well as in pets and livestock. In addition, the present invention relates to pharmaceutical compositions containing these compounds, as well as various uses thereof.

Abstract: A three-dimensional (3D) memory device includes a memory stack over a substrate. The memory stack includes interleaved conductor layers and insulating layers. The 3D memory device also includes channel structures extending vertically in the memory stack. The 3D memory device further includes a source structure extending in the memory stack. The source structure includes first and second source contacts separated by a support structure. The source structure also includes an adhesion layer. At least a portion of the adhesion layer is between the first and second source contacts and conductively connects the first and second source contacts.

Abstract: Embodiments of structure and methods for forming a three-dimensional (3D) memory device are provided. In an example, a 3D memory device includes a stack structure and at least one source structure extending vertically and laterally and dividing the stack structure into a plurality of block regions. The stack structure may include a plurality of conductor layers and a plurality of insulating layers interleaved over a substrate. The at least one source structure includes at least one support structure extending along the vertical direction to the substrate, the at least one support structure being in contact with at least a sidewall of the respective source structure.

Abstract: A method for forming a three-dimensional (3D) memory device is disclosed. In some embodiments, the method includes forming an alternating dielectric stack on a substrate, and forming a plurality of channel holes penetrating the alternating dielectric stack vertically to expose at least a portion of the substrate. A first mask can be formed to cover the channel holes in a first area and expose the channel holes in a second area. The method also includes forming a recess in the alternating dielectric stack in the second area, followed by forming a second mask in the recess. The second mask covers the channel holes in the second area and exposes the channel holes in the first area. The memory film at bottom of each channel hole in the first area can therefore be removed, while the memory film in the second area can be protected by the second mask.

Abstract: A three-dimensional (3D) memory device includes a memory stack over a substrate. The memory stack includes interleaved a plurality of conductor layers and a plurality of insulating layers. The 3D memory device also includes a plurality of channel structures extending vertically in the memory stack. The 3D memory device further includes a source structure extending in the memory stack. The source structure includes a support structure dividing the source structure into first and second sections. The source structure also includes an adhesion layer. At least a portion of the adhesion layer extends through the support structure and conductively connects the first and second sections.

Abstract: Embodiments of structure and methods for forming a three-dimensional (3D) memory device are provided. In an example, a method for forming a 3D memory device includes the following operations. A cut structure is first formed in a stack structure. The stack structure includes interleaved initial sacrificial layers and initial insulating layers. A patterned cap material layer is formed over the stack structure. The patterned cap material layer includes an opening over the cut structure. Portions of the stack structure and the patterned cap material layer adjacent to the opening are removed to form a slit structure and an initial support structure. The initial support structure divides the slit structure into slit openings. Conductor portions are formed through the plurality of slit openings to form a support structure. A source contact is formed in each slit opening. A connection layer is formed over the source contact in each slit opening and over the support structure.

Abstract: A method for forming a 3D memory device is provided. The method includes forming a dielectric stack including interleaved initial insulating layers and initial sacrificial layers over a substrate, and forming at least one slit structure extending vertically and laterally in the dielectric stack and dividing the dielectric stack into block regions. The at least one slit structure each includes slit openings exposing the substrate and an initial support structure between adjacent slit openings. Each block region may include interleaved insulating layers and sacrificial layers, and the initial support structure may include interleaved insulating portions and sacrificial portions. Each insulating portion and sacrificial portion may be in contact with respective insulating layers and sacrificial layers of a same level from adjacent block regions.

Abstract: A method for forming a three-dimensional (3D) memory device includes forming a cut structure in a stack structure. The stack structure includes interleaved a plurality of initial sacrificial layers and a plurality of initial insulating layers. The method also includes removing portions of the stack structure adjacent to the cut structure to form a slit structure and an initial support structure. The initial support structure divides the slit structure into a plurality of slit openings. The method further includes forming a plurality of conductor portions in the initial support structure through the plurality of slit openings. The method also includes forming a source contact in each of the plurality of slit openings. The method also includes removing portions of the initial support structure to form a support structure. The support structure includes an adhesion portion extending through the support structure.

Abstract: Embodiments of three-dimensional (3D) memory devices and fabricating methods thereof are disclosed. The method includes: forming an alternating dielectric stack on a substrate; forming a top selective gate cut and two structure strengthen plugs in an upper portion of the alternating dielectric stack, wherein each structure strengthen plug has a narrow support body and two enlarged connecting portions; forming a plurality of channel structures in the alternating dielectric stack; forming a plurality of gate line silts in the alternating dielectric stack, wherein each gate line slit exposes a sidewall of one enlarged connecting portion of a corresponding structure strengthen plug; transforming the alternating dielectric stack into an alternating conductive/dielectric stack; and forming a gate line slit structure in each gate line slit including an enlarged end portion connected to one enlarged connecting portion of a corresponding structure strengthen plug.

Abstract: A non-transitory computer-readable storage medium includes instructions for commissioning a power meter that has a Bluetooth Low Energy (BLE) communication capability, the instructions, when executed by one or more processors of a mobile device, cause the mobile device to discover the presence of the power meter by recognizing a signal produced by the Bluetooth Low Energy (BLE) communication capability of the power meter and receive a unique identifier for the power meter. When the received unique identifier matches a unique identifier stored by the power meter, the mobile device will establish a communication link between the mobile device and the power meter using the Bluetooth Low Energy (BLE) communication capability of the power meter and will transmit one or more commissioning parameters to the power meter via the established communication link between the mobile device and the power meter.

Abstract: A 3D memory structure, a 3D memory device and an electronic apparatus are disclosed and include a substrate having a recess, a 3D memory component with a bottom disposed in the recess of the substrate, and a peripheral circuit disposed on the substrate outside the recess.

Abstract: The present invention provides a high-resolution Micro-OLED display module and a manufacturing method thereof. The method for manufacturing the high-resolution Micro-OLED comprises: S1, providing a substrate, and manufacturing light-emitting pixel units on the substrate; S2, encapsulating the light-emitting pixel units by a film encapsulation technique, and forming a film encapsulation layer; S3, manufacturing sub-pixel units on the surface of the film encapsulation layer, and depositing a metal reflective layer between two sub-pixel units which are adjacent to each other; S4, manufacturing a metal oxide layer on the surfaces of the metal reflective layer and the sub-pixel units by a deposition technique, to obtain a high-resolution Micro-OLED matrix; and S5, using a cover plate to encapsulate the high-resolution Micro-OLED matrix produced in step S4, to finish the manufacturing of a high-resolution Micro-OLED.

Abstract: A power meter includes a plurality of terminals for receiving a measure of power consumption of each of one or more phases of power that is delivered to a load and a controller that is operatively coupled to the plurality of terminals. The controller is configured to determine a number of power monitor parameters based on the measure of power consumption of each of one or more phases of power that is delivered to the load. The controller is further configured to operate an interactive menu. The power meter includes a user interface that is configured to display the number of power monitor parameters based on the measure of power consumption of each of one or more phases of power that is delivered to the load and to enable a user to navigate the interactive menu using via one or more screens displayed on the user interface.

Abstract: Embodiments of structure and methods for forming a three-dimensional (3D) memory device are provided. In an example, a method for forming a 3D memory device includes forming a bottom select structure extending along a vertical direction through a bottom conductor layer over a substrate and along a horizontal direction to divide the bottom conductor layer into a pair of bottom select conductor layers, forming a plurality of conductor layers and a plurality of insulating layers interleaved on the pair of bottom select conductor layers and the bottom select structure, and forming a plurality of channel structures extending along the vertical direction through the pair of bottom select conductor layers, the plurality of conductor layers, and the plurality of insulating layers and into the substrate.

Abstract: Disclosed in the present invention are a pyrazolo [1,5-a]pyrimidine derivative having a structure of formula (I), a pharmaceutical composition comprising the compound of formula (I), and use of the compound in the preparation of a medicament for preventing or treating diseases associated with tropomyosin receptor kinases, in particular for preventing or treating cancers associated with tropomyosin receptor kinases. Each substituent in formula (I) has the same definition as that in the description.

Abstract: A method for manufacturing a three-dimensional (3D) memory structure and a 3D memory structure are disclosed. A recess is formed on a substrate, a 3D memory component is formed with a bottom in the recess, and then, a peripheral circuit is formed on the substrate outside the recess.

Abstract: A three-dimensional (3D) memory device includes a memory stack over a substrate. The memory stack includes interleaved a plurality of conductor layers and a plurality of insulating layers. The 3D memory device also includes a plurality of channel structures extending vertically in the memory stack. The 3D memory device further includes a source structure extending in the memory stack. The source structure includes a support structure dividing the source structure into first and second sections. The source structure also includes an adhesion layer. At least a portion of the adhesion layer extends through the support structure and conductively connects the first and second sections.

Abstract: A three-dimensional (3D) memory device includes a memory stack over a substrate. The memory stack includes interleaved conductor layers and insulating layers. The 3D memory device also includes channel structures extending vertically in the memory stack. The 3D memory device further includes a source structure extending in the memory stack. The source structure includes first and second source contacts separated by a support structure. The source structure also includes an adhesion layer. At least a portion of the adhesion layer is between the first and second source contacts and conductively connects the first and second source contacts.