Patents by Inventor Weng-Jin Wu

Weng-Jin Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • System, Structure, and Method of Manufacturing a Semiconductor Substrate Stack
    Publication number: 20150024546
    Abstract: A method of manufacturing a semiconductor substrate structure for use in a semiconductor substrate stack system is presented. The method includes a semiconductor substrate which includes a front-face, a backside, a bulk layer, an interconnect layer that includes a plurality of inter-metal dielectric layers sandwiched between conductive layers, a contact layer that is between the bulk layer and the interconnect layer, and a TSV structure commencing between the bulk layer and the contact layer and terminating at the backside of the substrate. The TSV structure is electrically coupled to the interconnect layer and the TSV structure is electrically coupled to a bonding pad on the backside.
    Type: Application
    Filed: October 6, 2014
    Publication date: January 22, 2015
    Inventors: Hung-Pin Chang, Weng-Jin Wu, Wen-Chih Chiou, Chen-Hua Yu
  • Alignment mark and method of formation
    Patent number: 8896136
    Abstract: In accordance with an embodiment, a structure comprises a substrate having a first area and a second area; a through substrate via (TSV) in the substrate penetrating the first area of the substrate; an isolation layer over the second area of the substrate, the isolation layer having a recess; and a conductive material in the recess of the isolation layer, the isolation layer being disposed between the conductive material and the substrate in the recess.
    Type: Grant
    Filed: June 30, 2010
    Date of Patent: November 25, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Yu Tsai, Shih-Hui Wang, Chien-Ming Chiu, Chia-Ho Chen, Fang Wen Tsai, Weng-Jin Wu, Jing-Cheng Lin, Wen-Chih Chiou, Shin-Puu Jeng, Chen-Hua Yu
  • System, structure, and method of manufacturing a semiconductor substrate stack
    Patent number: 8853830
    Abstract: A method of manufacturing a semiconductor substrate structure for use in a semiconductor substrate stack system is presented. The method includes a semiconductor substrate which includes a front-face, a backside, a bulk layer, an interconnect layer that includes a plurality of inter-metal dielectric layers sandwiched between conductive layers, a contact layer that is between the bulk layer and the interconnect layer, and a TSV structure commencing between the bulk layer and the contact layer and terminating at the backside of the substrate. The TSV structure is electrically coupled to the interconnect layer and the TSV structure is electrically coupled to a bonding pad on the backside.
    Type: Grant
    Filed: July 23, 2008
    Date of Patent: October 7, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Pin Chang, Weng-Jin Wu, Wen-Chih Chiou, Chen-Hua Yu
  • Process of forming through-silicon via structure
    Patent number: 8846523
    Abstract: In a process, an opening is formed to extend from a front surface of a semiconductor substrate through at least a part of the semiconductor substrate. A metal seed layer is formed on a sidewall of the opening. A metal silicide layer is formed on at least one portion of the metal seed layer. A metal layer is formed on the metal silicide layer and the metal seed layer to fill the opening.
    Type: Grant
    Filed: April 1, 2013
    Date of Patent: September 30, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Weng-Jin Wu, Yung-Chi Lin, Wen-Chih Chiou
  • Composite carrier structure
    Patent number: 8846499
    Abstract: A composite carrier structure for manufacturing semiconductor devices is provided. The composite carrier structure utilizes multiple carrier substrates, e.g., glass or silicon substrates, coupled together by interposed adhesive layers. The composite carrier structure may be attached to a wafer or a die for, e.g., backside processing, such as thinning processes. In an embodiment, the composite carrier structure comprises a first carrier substrate having through-substrate vias formed therethrough. The first substrate is attached to a second substrate using an adhesive such that the adhesive may extend into the through-substrate vias.
    Type: Grant
    Filed: August 17, 2010
    Date of Patent: September 30, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ying-Ching Shih, Weng-Jin Wu, Jing-Cheng Lin, Wen-Chih Chiou, Shin-Puu Jeng, Chen-Hua Yu
  • Backside Through Vias in a Bonded Structure
    Publication number: 20140232013
    Abstract: A wafer thinning system and method are disclosed that includes grinding away substrate material from a backside of a semiconductor device. A current change is detected in a grinding device responsive to exposure of a first set of device structures through the substrate material, where the grinding is stopped in response to the detected current change. Polishing repairs the surface and continues to remove an additional amount of the substrate material. Exposure of one or more additional sets of device structures through the substrate material is monitored to determine the additional amount of substrate material to remove, where the additional sets of device structures are located in the semiconductor device at a known depth different than the first set.
    Type: Application
    Filed: April 28, 2014
    Publication date: August 21, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Weng-Jin Wu, Ku-Feng Yang, Hung-Pin Chang, Wen-Chih Chiou, Chen-Hua Yu
  • STACKED STRUCTURES AND METHODS OF FORMING STACKED STRUCTURES
    Publication number: 20140220741
    Abstract: A stacked structure includes a first die bonded over a second die. The first die has a first die area defined over a first surface. At least one first protective structure is formed over the first surface, around the first die area. At least one side of the first protective structure has at least one first extrusion part extending across a first scribe line around the protective structure. The second die has a second die area defined over a second surface. At least one second protective structure is formed over the second surface, around the second die area. At least one side of the second protective structure has at least one second extrusion part extending across a second scribe line around the protective structure, wherein the first extrusion part is connected with the second extrusion part.
    Type: Application
    Filed: April 14, 2014
    Publication date: August 7, 2014
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Weng-Jin WU, Wen-Chih CHIOU, Chen-Hua YU
  • Through-silicon via structure formation process
    Patent number: 8791011
    Abstract: In a process, an opening is formed to extend from a front surface of a semiconductor substrate through a part of the semiconductor substrate. A metal seed layer is formed on a sidewall of the opening. A block layer is formed on only a portion of the metal seed layer. A metal layer is formed on the block layer and the metal seed layer to fill the opening.
    Type: Grant
    Filed: February 25, 2013
    Date of Patent: July 29, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yung-Chi Lin, Weng-Jin Wu, Shau-Lin Shue
  • Barrier for Through-Silicon Via
    Publication number: 20140175652
    Abstract: A system and a method for protecting vias is disclosed. An embodiment comprises forming an opening in a substrate. A barrier layer disposed in the opening including along the sidewalls of the opening. The barrier layer may include a metal component and an alloying material. A conductive material is formed on the barrier layer and fills the opening. The conductive material to form a via (e.g., TSV).
    Type: Application
    Filed: February 26, 2014
    Publication date: June 26, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chen-Hua Yu, Wen-Chih Chiou, Weng-Jin Wu
  • Stacked structures and methods of forming stacked structures
    Patent number: 8736039
    Abstract: A stacked structure includes a first die bonded over a second die. The first die has a first die area defined over a first surface. At least one first protective structure is formed over the first surface, around the first die area. At least one side of the first protective structure has at least one first extrusion part extending across a first scribe line around the protective structure. The second die has a second die area defined over a second surface. At least one second protective structure is formed over the second surface, around the second die area. At least one side of the second protective structure has at least one second extrusion part extending across a second scribe line around the protective structure, wherein the first extrusion part is connected with the second extrusion part.
    Type: Grant
    Filed: October 6, 2006
    Date of Patent: May 27, 2014
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Weng-Jin Wu, Wen-Chih Chiou, Chen-Hua Yu
  • Controlling defects in thin wafer handling
    Patent number: 8722540
    Abstract: A method includes bonding a wafer on a carrier through an adhesive, and performing a thinning process on the wafer. After the step of performing the thinning process, a portion of the adhesive not covered by the wafer is removed, while the portion of the adhesive covered by the wafer is not removed.
    Type: Grant
    Filed: July 22, 2010
    Date of Patent: May 13, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Liang Lin, Weng-Jin Wu, Jing-Cheng Lin
  • Barrier structures and methods for through substrate vias
    Patent number: 8704375
    Abstract: Through substrate via barrier structures and methods are disclosed. In one embodiment, a semiconductor device includes a first substrate including an active device region disposed within isolation regions. A through substrate via is disposed adjacent to the active device region and within the first substrate. A buffer layer is disposed around at least a portion of the through substrate via, wherein the buffer layer is disposed between the isolation regions and the through substrate via.
    Type: Grant
    Filed: November 5, 2009
    Date of Patent: April 22, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Max Liu, Chao-Shun Hsu, Ya-Wen Tseng, Wen-Chih Chiou, Weng-Jin Wu
  • Backside process for a substrate
    Patent number: 8691664
    Abstract: A method of forming a semiconductor device is presented. A conductor is embedded within a substrate, wherein the substrate contains a non-conducting material. The backside of the substrate is ground to a thickness wherein at least 1 ?m of the non-conducting material remains on the backside covering the conductor embedded within the substrate. Chemical mechanical polishing (CMP) is employed with an undiscerning slurry to the backside of the substrate, thereby planarizing the substrate and exposing the conductive material. A spin wet-etch, with a protective formulation, is employed to remove a thickness y of the non-conducting material from the backside of the substrate, thereby causing the conductive material to uniformly protrude from the backside of the substrate.
    Type: Grant
    Filed: January 11, 2010
    Date of Patent: April 8, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ku-Feng Yang, Weng-Jin Wu, Wen-Chih Chiou, Jung-Chih Hu
  • Barrier for through-silicon via
    Patent number: 8680682
    Abstract: A system and a method for protecting vias is disclosed. An embodiment comprises forming an opening in a substrate. A barrier layer disposed in the opening including along the sidewalls of the opening. The barrier layer may include a metal component and an alloying material. A conductive material is formed on the barrier layer and fills the opening. The conductive material to form a via (e.g., TSV).
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: March 25, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Wen-Chih Chiou, Weng-Jin Wu
  • Multi-die stacking using bumps with different sizes
    Patent number: 8669174
    Abstract: A device includes a first die having a first side and a second side opposite to first side, the first side includes a first region and a second region, and a first metal bump of a first horizontal size formed on the first region of the first side of the first die. A second die is bonded to the first metal bump at the first side of the first die. A dielectric layer is formed over the first side of the first die and includes a first portion directly over the second die, a second portion covering the second die. A second metal bump of a second horizontal size greater than the first horizontal size is formed on the second region of the first side of the first die. An electrical component is bonded to the first side of the first die through the second metal bump.
    Type: Grant
    Filed: January 2, 2013
    Date of Patent: March 11, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Weng-Jin Wu, Ying-Ching Shih, Wen-Chih Chiou, Shin-Puu Jeng, Chen-Hua Yu
  • Component stacking using pre-formed adhesive films
    Patent number: 8664749
    Abstract: A method of forming integrated circuits includes laminating a patterned film including an opening onto a wafer, wherein a bottom die in the wafer is exposed through the opening. A top die is placed into the opening. The top die fits into the opening with substantially no gap between the patterned film and the top die. The top die is then bonded onto the bottom die, followed by curing the patterned film.
    Type: Grant
    Filed: April 11, 2011
    Date of Patent: March 4, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Weng-Jin Wu, Hung-Jung Tu, Ku-Feng Yang, Jung-Chih Hu, Wen-Chih Chiou
  • Surface modification for handling wafer thinning process
    Patent number: 8647925
    Abstract: A wafer is provided with a through via extending a portion of a substrate, an interconnect structure electrically connecting the through via, and a polyimide layer formed on the interconnect structure. Surface modification of the polyimide layer is the formation of a thin dielectric film on the polyimide layer by coating, plasma treatment, chemical treatment, or deposition methods. The thin dielectric film is adhered strongly to the polyimide layer, which can reduce the adhesion between the wafer surface and an adhesive layer formed in subsequent carrier attaching process.
    Type: Grant
    Filed: June 3, 2010
    Date of Patent: February 11, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Chih Chiou, Shau-Lin Shue, Weng-Jin Wu, Ju-Pin Hung
  • Method for stacking semiconductor dies
    Patent number: 8629042
    Abstract: A system and method for stacking semiconductor dies is disclosed. A preferred embodiment comprises forming through-silicon vias through the wafer, protecting a rim edge of the wafer, and then removing the unprotected portions so that the rim edge has a greater thickness than the thinned wafer. This thickness helps the fragile wafer survive further transport and process steps. The rim edge is then preferably removed during singulation of the individual dies from the wafer.
    Type: Grant
    Filed: January 23, 2013
    Date of Patent: January 14, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ku-Feng Yang, Weng-Jin Wu, Wen-Chih Chiou, Chen-Hua Yu
  • Thin wafer protection device
    Patent number: 8629565
    Abstract: A thin wafer protection device includes a wafer having a plurality of semiconductor chips. The wafer has a first side and an opposite second side. A plurality of dies is over the first side of the wafer, and at least one of the plurality of dies is bonded to at least one of the plurality of semiconductor chips. A wafer carrier is over the second side of the wafer. An encapsulating layer is over the first side of the wafer and the plurality of dies, and the encapsulating layer has a planar top surface. An adhesive tape is over the planar top surface of the encapsulating layer.
    Type: Grant
    Filed: March 13, 2012
    Date of Patent: January 14, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ku-Feng Yang, Weng-Jin Wu, Wen-Chih Chiou, Tsung-Ding Wang
  • Apparatus and Method of Substrate to Substrate Bonding for Three Dimensional (3D) IC Interconnects
    Publication number: 20130320071
    Abstract: An apparatus including a bond head, a supplemental support, a reduction module, and a transducer is provided. The bond head holds a first substrate that contains a first set of metal pads. The supplemental support holds a second substrate that contains a second set of metal pads. The aligner forms an aligned set of metal pads by aligning the first substrate to the second substrate. The reduction module contains the aligned substrates and a reduction gas flows into the reduction module. The transducer provides repeated relative motion to the aligned set of metal pads.
    Type: Application
    Filed: August 8, 2013
    Publication date: December 5, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Wen-Chih Chiou, Weng-Jin Wu