Abstract: Implementations of semiconductor packages may include: a semiconductor device included within a cavity within a glass block. The package may also include a substrate coupled with a first side of the semiconductor device and two or more edges of the glass block. A fill material may be included between the substrate and the second conductor device and an opaque material may be between a side surface of the semiconductor device and an inner surface of the cavity. The opaque material may be configured to block light from contacting the side surface of the semiconductor device.

Abstract: A method of manufacturing a semiconductor substrate structure for use in a semiconductor substrate stack system is presented. The method includes a semiconductor substrate which includes a front-face, a backside, a bulk layer, an interconnect layer that includes a plurality of inter-metal dielectric layers sandwiched between conductive layers, a contact layer that is between the bulk layer and the interconnect layer, and a TSV structure commencing between the bulk layer and the contact layer and terminating at the backside of the substrate. The TSV structure is electrically coupled to the interconnect layer and the TSV structure is electrically coupled to a bonding pad on the backside.

Abstract: An embedded image sensor package including a transparent cover having a first side and an opposing second side. A first layer couples over the second side of the transparent cover and has an opening. An electrically conductive layer couples in or over the first layer and electrically couples with one or more electrical contacts exposed on an outer surface of the package. An image sensor chip having a first side with an image sensor and an opposing second side electrically couples with the electrically conductive layer at the first side of the image sensor chip. The image sensor chip couples over the first layer so the first side of the image sensor chip faces the second side of the transparent cover through the opening. The image sensor chip, first layer, and transparent cover at least partially define a cavity hermetically sealed using an underfill material. The package includes no wirebonds.

Abstract: According to an aspect, a sensor packaging structure includes a sensor die having a first surface and a second surface opposite the first surface, where the sensor die defines a sensor edge disposed between the first surface and the second surface. The sensor packaging structure includes a bonding material having a first surface and a second surface opposite the second surface, where the bonding material defines a bonding material edge disposed between the first surface of the bonding material and the second surface of the bonding material. The sensor packaging structure includes a transparent material, where the bonding material couples the sensor die to the transparent material. The sealing material is disposed on an interface between the sensor die and the bonding material, and at least one of a portion of the sensor edge or a portion of the bonding material edge.

Abstract: A method of manufacturing a semiconductor substrate structure for use in a semiconductor substrate stack system is presented. The method includes a semiconductor substrate which includes a front-face, a backside, a bulk layer, an interconnect layer that includes a plurality of inter-metal dielectric layers sandwiched between conductive layers, a contact layer that is between the bulk layer and the interconnect layer, and a TSV structure commencing between the bulk layer and the contact layer and terminating at the backside of the substrate. The TSV structure is electrically coupled to the interconnect layer and the TSV structure is electrically coupled to a bonding pad on the backside.

Abstract: Implementations of semiconductor packages may include: an image sensor; an optically transmissive transparent coating directly coupled to the image sensor; and a glass lid coupled directly coupled to the optically transmissive coating. An entire surface of the glass may be directly coupled to an entire surface of the optically transmissive adhesive coating.

Abstract: Implementations of semiconductor packages may include: an image sensor; an optically transmissive transparent coating directly coupled to the image sensor; and a glass lid coupled directly coupled to the optically transmissive coating. An entire surface of the glass may be directly coupled to an entire surface of the optically transmissive adhesive coating.

Abstract: Implementations of semiconductor packages may include: an image sensor; an optically transmissive transparent coating directly coupled to the image sensor; and a glass lid coupled directly coupled to the optically transmissive coating. An entire surface of the glass may be directly coupled to an entire surface of the optically transmissive adhesive coating.

Abstract: An image sensor semiconductor package (package) includes a printed circuit board (PCB) having a first surface and a second surface opposite the first surface. A complementary metal-oxide semiconductor (CMOS) image sensor (CIS) die has a first surface with a photosensitive region and a second surface opposite the first surface of the CIS die. The second surface of the CIS die is coupled with the first surface of the PCB. A transparent cover is coupled over the photosensitive region of the CIS die. An image signal processor (ISP) is embedded within the PCB. One or more electrical couplers electrically couple the CIS die with the PCB. A plurality of electrical contacts on the second surface of the PCB are electrically coupled with the CIS die and with the ISP. The ISP is located between the plurality of electrical contacts of the second surface of the PCB and the CIS die.

Abstract: An image sensor semiconductor package (package) includes a printed circuit board (PCB) having a first surface and a second surface opposite the first surface. A complementary metal-oxide semiconductor (CMOS) image sensor (CIS) die has a first surface with a photosensitive region and a second surface opposite the first surface of the CIS die. The second surface of the CIS die is coupled with the first surface of the PCB. A transparent cover is coupled over the photosensitive region of the CIS die. An image signal processor (ISP) is embedded within the PCB. One or more electrical couplers electrically couple the CIS die with the PCB. A plurality of electrical contacts on the second surface of the PCB are electrically coupled with the CIS die and with the ISP. The ISP is located between the plurality of electrical contacts of the second surface of the PCB and the CIS die.

Abstract: An embedded image sensor package including a transparent cover having a first side and an opposing second side. A first layer couples over the second side of the transparent cover and has an opening. An electrically conductive layer couples in or over the first layer and electrically couples with one or more electrical contacts exposed on an outer surface of the package. An image sensor chip having a first side with an image sensor and an opposing second side electrically couples with the electrically conductive layer at the first side of the image sensor chip. The image sensor chip couples over the first layer so the first side of the image sensor chip faces the second side of the transparent cover through the opening. The image sensor chip, first layer, and transparent cover at least partially define a cavity hermetically sealed using an underfill material. The package includes no wirebonds.

Abstract: An embedded image sensor package including a transparent cover having a first side and an opposing second side. A first layer couples over the second side of the transparent cover and has an opening. An electrically conductive layer couples in or over the first layer and electrically couples with one or more electrical contacts exposed on an outer surface of the package. An image sensor chip having a first side with an image sensor and an opposing second side electrically couples with the electrically conductive layer at the first side of the image sensor chip. The image sensor chip couples over the first layer so the first side of the image sensor chip faces the second side of the transparent cover through the opening. The image sensor chip, first layer, and transparent cover at least partially define a cavity hermetically sealed using an underfill material. The package includes no wirebonds.

Abstract: An embedded image sensor package including a transparent cover having a first side and an opposing second side. A first layer couples over the second side of the transparent cover and has an opening. An electrically conductive layer couples in or over the first layer and electrically couples with one or more electrical contacts exposed on an outer surface of the package. An image sensor chip having a first side with an image sensor and an opposing second side electrically couples with the electrically conductive layer at the first side of the image sensor chip. The image sensor chip couples over the first layer so the first side of the image sensor chip faces the second side of the transparent cover through the opening. The image sensor chip, first layer, and transparent cover at least partially define a cavity hermetically sealed using an underfill material. The package includes no wirebonds.

Abstract: Implementations of a molded image sensor chip scale package may include an image sensor having a first side and a second side. A first cavity wall and a second cavity wall may be coupled to the first side of the image sensor and extend therefrom. The first cavity wall and the second cavity wall may form a cavity over the image sensor. A transparent layer may be coupled to the first cavity wall and the second cavity wall. A redistribution layer (RDL) may be coupled to the second side of the image sensor. At least one interconnect may be directly coupled to the RDL. A mold material may encapsulate a portion of the RDL, a portion of the image sensor, and a side of each cavity wall, and a portion of the transparent layer.

Abstract: A three-dimensional integrated circuit (3DIC) including a first substrate having a first surface and a second surface opposite to the first surface and a second substrate attached to the first surface of the first substrate. The 3DIC further includes an interconnect between attached to the first surface of the first substrate and the second substrate and a plurality of through vias formed in the first substrate and electrically coupled to the interconnect. The 3DIC further includes a protection layer over the second surface of the first substrate, wherein each of the plurality of through vias protrudes through the protection layer and a plurality of dies, each die of the plurality of dies attached to at least one through via of the plurality of through vias.

Abstract: A method of wafer bonding includes bonding a wafer to a carrier in a bonding system. The method further includes measuring thickness profile of the bonded wafer. The method further includes modifying surface contours of at least one of an upper plate or a lower plate of the bonding system during a bonding operation to improve planarity of bonded wafers based on the measured thickness profile, wherein modifying the surface contours of at least one of the upper plate or the lower plate comprises modifying the surface contours using a plurality of height adjusters.

Abstract: Implementations of a molded image sensor chip scale package may include an image sensor having a first side and a second side. A first cavity wall and a second cavity wall may be coupled to the first side of the image sensor and extend therefrom. The first cavity wall and the second cavity wall may form a cavity over the image sensor. A transparent layer may be coupled to the first cavity wall and the second cavity wall. A redistribution layer (RDL) may be coupled to the second side of the image sensor. At least one interconnect may be directly coupled to the RDL. A mold material may encapsulate a portion of the RDL, a portion of the image sensor, and a side of each cavity wall, and a portion of the transparent layer.

Abstract: An embedded image sensor package including a transparent cover having a first side and an opposing second side. A first layer couples over the second side of the transparent cover and has an opening. An electrically conductive layer couples in or over the first layer and electrically couples with one or more electrical contacts exposed on an outer surface of the package. An image sensor chip having a first side with an image sensor and an opposing second side electrically couples with the electrically conductive layer at the first side of the image sensor chip. The image sensor chip couples over the first layer so the first side of the image sensor chip faces the second side of the transparent cover through the opening. The image sensor chip, first layer, and transparent cover at least partially define a cavity hermetically sealed using an underfill material. The package includes no wirebonds.

Abstract: An image sensor semiconductor package (package) includes a printed circuit board (PCB) having a first surface and a second surface opposite the first surface. A complementary metal-oxide semiconductor (CMOS) image sensor (CIS) die has a first surface with a photosensitive region and a second surface opposite the first surface of the CIS die. The second surface of the CIS die is coupled with the first surface of the PCB. A transparent cover is coupled over the photosensitive region of the CIS die. An image signal processor (ISP) is embedded within the PCB. One or more electrical couplers electrically couple the CIS die with the PCB. A plurality of electrical contacts on the second surface of the PCB are electrically coupled with the CIS die and with the ISP. The ISP is located between the plurality of electrical contacts of the second surface of the PCB and the CIS die.

Abstract: A wafer thinning system and method are disclosed that includes grinding away substrate material from a backside of a semiconductor device. A current change is detected in a grinding device responsive to exposure of a first set of device structures through the substrate material, where the grinding is stopped in response to the detected current change. Polishing repairs the surface and continues to remove an additional amount of the substrate material. Exposure of one or more additional sets of device structures through the substrate material is monitored to determine the additional amount of substrate material to remove, where the additional sets of device structures are located in the semiconductor device at a known depth different than the first set.