Abstract: A device includes a first die having a first side and a second side opposite to first side, the first side includes a first region and a second region, and a first metal bump of a first horizontal size formed on the first region of the first side of the first die. A second die is bonded to the first side of the first die through the first metal bump. A dielectric layer is formed over the first side of the first die and includes a first portion directly over the second die, a second portion encircling the second die, and an opening exposing the second region of the first side of the first die. A second metal bump of a second horizontal size is formed on the second region of the first side of the first die and extending into the opening of the dielectric layer. The second horizontal size is greater than the first horizontal size. An electrical component is bonded to the first side of the first die through the second metal bump.

Abstract: A semiconductor component having a semiconductor substrate including an integrated circuit (IC) component, an interlayer dielectric (ILD) layer formed on the semiconductor substrate, a contact plug formed in the ILD layer and electrically connected to the IC component, a via plug formed in the ILD layer and extending through a portion of the semiconductor substrate, wherein the top surfaces of the ILD layer, the via plug and the contact plug are leveled off, and an interconnection structure comprising a plurality of metal layers formed in a plurality of inter-metal dielectric (IMD) layers, wherein a lowermost metal layer of the interconnection structure is electrically connected to the exposed portions of the contact plug and the via plug.

Abstract: An apparatus including a bond head, a supplemental support, a reduction module, and a transducer is provided. The bond head holds a first substrate that contains a first set of metal pads. The supplemental support holds a second substrate that contains a second set of metal pads. The aligner forms an aligned set of metal pads by aligning the first substrate to the second substrate. The reduction module contains the aligned substrates and a reduction gas flows into the reduction module. The transducer provides repeated relative motion to the aligned set of metal pads.

Abstract: An apparatus for supporting a wafer includes a base, and a gas-penetration layer. The gas-penetration layer and a portion of the base directly underlying the gas-penetration layer form a gas passage therebetween. The gas passage is configured to be sealed by the wafer placed directly over the gas-penetration layer. The apparatus further includes a valve connected to the gas passage.

Abstract: A through via process is performed on a semiconductor substrate with a contact plug formed in an interlayer dielectric (ILD), and then a via plug is formed in the ILD layer to extend through a portion of the semiconductor substrate, followed forming an interconnection structure electrically connected with the contact plug and the via plug.

Abstract: In a process, an opening is formed to extend from a front surface of a semiconductor substrate through a part of the semiconductor substrate. A metal seed layer is formed on a sidewall of the opening. A block layer is formed on only a portion of the metal seed layer. A metal layer is formed on the block layer and the metal seed layer to fill the opening.

Abstract: This description relates to a semiconductor device including a wafer having a first surface and a second surface opposite to the first surface and a carrier attached to the first surface of the wafer by an adhesive layer, a portion of the adhesive layer adjacent to an edge of the wafer is exposed. The semiconductor device further includes a protection layer to cover the exposed portion of the adhesive layer. The semiconductor device further includes a plurality of dies attached to the second surface and a molding compound encapsulating the plurality of dies.

Abstract: A through-silicon via (TSV) structure and process for forming the same are disclosed. A semiconductor substrate has a front surface and a back surface, and a TSV structure is formed to extend through the semiconductor substrate. The TSV structure includes a metal layer, a metal seed layer surrounding the metal layer, a barrier layer surrounding the metal seed layer, and a metal silicide layer formed in a portion sandwiched between the metal layer and the metal seed layer.

Abstract: A method for fabricating three dimensional integrated circuits comprises providing a wafer stack wherein a plurality of semiconductor dies are mounted on a first semiconductor die, forming a molding compound layer on the first side of the first semiconductor die, wherein the plurality of semiconductor dies are embedded in the molding compound layer. The method further comprises grinding a second side of the first semiconductor die until a plurality of through vias become exposed, attaching the wafer stack to a tape frame and dicing the wafer stack to separate the wafer stack into a plurality of individual packages.

Abstract: A semiconductor structure includes a first die comprising a first substrate and a first bonding pad over the first substrate, a second die having a first surface and a second surface opposite the first surface, wherein the second die is stacked on the first die and a protection layer having a vertical portion on a sidewall of the second die, and a horizontal portion extending over the first die.

Abstract: A semiconductor substrate has a front surface and a back surface, and a TSV structure is formed to extend through the semiconductor substrate. The TSV structure includes a metal layer, a metal seed layer surrounding the metal layer, a barrier layer surrounding the metal seed layer, and a block layer formed in a portion sandwiched between the metal layer and the metal seed layer. The block layer includes magnesium (Mg), iron (Fe), cobalt (Co), nickel (Ni), titanium (Ti), chromium (Cr), tantalum (Ta), tungsten (W), cadmium (Cd), or combinations thereof.

Abstract: A method of fabricating a three-dimensional integrated circuit comprises attaching a wafer to a carrier, mounting a plurality of semiconductor dies on top of the wafer to form a wafer stack. The method further comprises forming a molding compound layer on top of the wafer, attaching the wafer stack to a tape frame and dicing the wafer stack to separate the wafer stack into a plurality of individual packages.

Abstract: The present disclosure provides a bonding apparatus. The bonding apparatus includes a cleaning module designed for cleaning chips; and a chip-to-wafer bonding chamber configured to receive the chips from the cleaning module and designed for bonding the chips to a wafer.

Abstract: A system and method for stacking semiconductor dies is disclosed. A preferred embodiment comprises forming through-silicon vias through the wafer, protecting a rim edge of the wafer, and then removing the unprotected portions so that the rim edge has a greater thickness than the thinned wafer. This thickness helps the fragile wafer survive further transport and process steps. The rim edge is then preferably removed during singulation of the individual dies from the wafer.

Abstract: A system and a method for protecting through-silicon vias (TSVs) is disclosed. An embodiment comprises forming an opening in a substrate. A liner is formed in the opening and a barrier layer comprising carbon or fluorine is formed along the sidewalls and bottom of the opening. A seed layer is formed over the barrier layer, and the TSV opening is filled with a conductive filler. Another embodiment includes a barrier layer formed using atomic layer deposition.

Abstract: This description relates to a semiconductor device including a wafer having a first surface and a second surface opposite to the first surface and a carrier attached to the first surface of the wafer by an adhesive layer, a portion of the adhesive layer adjacent to an edge of the wafer is exposed. The semiconductor device further includes a protection layer to cover the exposed portion of the adhesive layer. The semiconductor device further includes a plurality of dies attached to the second surface and a molding compound encapsulating the plurality of dies.

Abstract: An integrated circuit structure includes a semiconductor substrate having a front side and a backside. A through-silicon via (TSV) penetrates the semiconductor substrate. The TSV has a back end extending to the backside of the semiconductor substrate. A redistribution line (RDL) is over the backside of the semiconductor substrate and connected to the back end of the TSV. A silicide layer is over and contacting the RDL.

Abstract: A method for thinning a wafer is provided. In one embodiment, a wafer is provided having a plurality of semiconductor chips, the wafer having a first side and a second side opposite the first side, wherein each of the chips includes a set of through silicon vias (TSVs), each of the TSVs substantially sealed by a liner layer and a barrier layer. A wafer carrier is provided for attaching to the second side of the wafer. The first side of the wafer is thinned and thereafer recessed to partially expose portions of the liner layers, barrier layers and the TSVs protruding from the wafer. An isolation layer is deposited over the first side of the wafer and the top portions of the liner layers, barrier layers and the TSVs. Thereafter, an insulation layer is deposited over the isolation layer. The insulation layer is then planarized to expose top portions of the TSVs. A dielectric layer is deposited over the planarized first side of the wafer.

Abstract: A wafer is attached to a carrier by using an adhesive layer, and a portion of the adhesive layer is exposed adjacent to an edge of the wafer. After thinning the wafer, a protection layer is provided to cover the exposed portion of the adhesive layer. A plurality of dies is bonded onto the thinned wafer, and then the thinned wafer and the dies are encapsulated with a molding compound.

Abstract: A method for thin wafer handling and processing is provided. In one embodiment, the method comprises providing a wafer having a plurality of semiconductor chips, the wafer having a first side and a second side. A plurality of dies are attached to the first side of the wafer, at least one of the dies are bonded to at least one of the plurality of semiconductor chips. A wafer carrier is provided, wherein the wafer carrier is attached to the second side of the wafer. The first side of the wafer and the plurality of dies are encapsulated with a planar support layer. A first adhesion tape is attached to the planar support layer. The wafer carrier is then removed from the wafer and the wafer is diced into individual semiconductor packages.