Abstract: A data processing method, applied to an applet, includes: sending a plug-in service request to a platform server, the plug-in service request comprising a plug-in identifier configured for the platform server to establish a usage association between a plug-in corresponding to the plug-in identifier and the applet, wherein the plug-in has an independent data server; receiving an applet access request, determining whether the applet access request and a service corresponding to the plug-in meet a preset correspondence, and if it is determined that the applet access request and the service corresponding to the plug-in meet the preset correspondence, loading the plug-in according to the usage association; and sending the applet access request to the plug-in, so that the plug-in completes a task corresponding to the applet access request by accessing the data server of the plug-in.

Abstract: A detachable capacitor connection structure is provided for a storage device. In an embodiment, a connection element detachably connects a capacitor module including one or more capacitors to a circuit board such that the capacitor module is stacked over the circuit board. The connection element includes: a first connector including two pin headers, mounted on a bottom plane of the capacitor module; and a second connector including two sockets, mounted on a top plane of the circuit board corresponding to the bottom of the capacitor module, suitable for connecting the first connector to the circuit board.

Abstract: Circuits integrating OR logic and level shifting functionality and methods of operating the same are configured to accommodate different applications. One such circuit comprises first and second transistors coupled in parallel defining first and second nodes, the first transistor being responsive to a first input signal and the second transistor being responsive to a second input signal; a first resistor coupled between a power supply terminal of the circuit and the first node; and a second resistor coupled between the second node and a ground terminal of the circuit. The circuit generates an output signal having a voltage level that is lower than a voltage level of each of the first and second input signals.

Abstract: Noise injection systems and methods for conducting power noise susceptibility tests on memory systems, including solid state drives. A noise injection system comprises a power selector to deliver a voltage at a first or second level according to a frequency level indicated by a frequency select signal; a noise signal relay to receive a frequency noise signal and to deliver a low or high frequency noise component of the frequency noise signal according to the frequency level of the frequency select signal; and an amplification assembly, responsive to the frequency select signal and which receives the first or second level voltage based on the frequency level of the frequency select signal, receives and amplifies the high frequency noise component when the frequency select signal indicates a high frequency level, and receives and amplifies the low frequency noise component when the frequency select signal indicates a low frequency level.

Abstract: Circuits integrating OR logic and level shifting functionality and methods of operating the same are configured to accommodate different applications. One such circuit comprises first and second transistors coupled in parallel defining first and second nodes, the first transistor being responsive to a first input signal and the second transistor being responsive to a second input signal; a first resistor coupled between a power supply terminal of the circuit and the first node; and a second resistor coupled between the second node and a ground terminal of the circuit. The circuit generates an output signal having a voltage level that is lower than a voltage level of each of the first and second input signals.

Abstract: Techniques related to monitoring a health of a capacitor array of an SSD are described. In an example, a direct leakage current check is performed by determining voltages of the capacitor array at different times, computing a resistance of the capacitor array based on the voltages, and generating health data for the capacitor array based on the resistance. In another example, an indirect leakage current check is performed by determining at least one of: a number of times a voltage maintaining process is performed within a predefined time duration or a time difference between repeating the voltage maintaining process, comparing the at least one of the number of times or the time difference and a threshold, and generating the health data based on the comparison of the at least one of the number of times or the time difference and the threshold.

Abstract: Disclosed are a Z-N catalyst for ?-olefin polymerization and an application thereof, specifically, an industrial production catalyst consisting of (A) a solid catalyst component, (B) a cocatalyst organoaluminum compound and (C) an external electron donor compound and used for ?-olefin polymerization or copolymerization processes. The catalyst component is prepared from a transition metal such as titanium and magnesium and a composite aromatic diacid diester/1,3-diether as an internal electron donor. One or more organoaluminum compounds or a mixture thereof serve as the cocatalyst. One or more structure control agent hydrocarbyl alkoxysilicons are compounded with one or more activity regulator organic acid esters as the external electron donor capable of automatically adjusting the polymerization rate. The Z-N catalyst is used for ?-olefin polymerization/copolymerization, and can automatically adjust the polymerization rate at a higher polymerization temperature so as to maintain stable operation of a reactor.

Abstract: Solid-state mass storage devices and methods of operation thereof include a solid-state mass storage device that may have a capacitor-based power supply module configured for providing power to the mass storage device. In one embodiment, the mass storage device has a first mode of operation wherein a primary power supply provided by a host system provides power to the mass storage device sufficient for its operation and provides power to the capacitor-based power supply module to recharge the module, and a second mode of operation wherein power is provided to the mass storage device from both the primary power supply and the capacitor-based power supply module. The mass storage device may be capable of providing power from the capacitor-based power supply module to the mass storage device after a voltage level of the capacitor-based power supply module falls below an under voltage lock out level.

Abstract: Solid-state mass storage devices and methods of operation thereof include a solid-state mass storage device that may have a capacitor-based power supply module configured for providing power to the mass storage device. In one embodiment, the mass storage device has a first mode of operation wherein a primary power supply provided by a host system provides power to the mass storage device sufficient for its operation and provides power to the capacitor-based power supply module to recharge the module, and a second mode of operation wherein power is provided to the mass storage device from both the primary power supply and the capacitor-based power supply module. The mass storage device may be capable of providing power from the capacitor-based power supply module to the mass storage device after a voltage level of the capacitor-based power supply module falls below an under voltage lock out level.

Abstract: An apparatus and methods to fabricate the apparatus for balancing a string of N series-connected electrical energy units (such as battery cells or modules) comprising: a transformer with a magnetic core and N windings; N switch circuits; N driver circuits, each driver circuit operable to turn ON/OFF a respective switch circuit in a discharging or charging or idling configuration; and a controller circuit.

Abstract: A system and method thereof to regulate a current to a capacitive load from a power supply connected to the capacitive load. The system includes a first switch between the power supply and the capacitive load, a super-capacitor configured for charging by the power supply and powering the capacitive load, a current limiting circuit between the super-capacitor and the power supply, a second switch between the super-capacitor and the capacitive load, and a power control circuit configured to control opening and closing of the first switch and the second switch independently, sense a voltage of the power supply, and sense a voltage of the super-capacitor.

Abstract: An apparatus and methods to fabricate the apparatus for balancing a string of N series-connected electrical energy units (such as battery cells or modules) comprising: a transformer with a magnetic core and N windings; N switch circuits; N driver circuits, each driver circuit operable to turn ON/OFF a respective switch circuit in a charging or discharging or idling configuration; and a controller circuit.

Abstract: A level shifter for level-shifting a digital input signal referenced to an input ground potential to a digital output signal referenced to an output ground potential, comprising: a capacitor; a driver circuit, including an input node coupled to the digital input signal, and an output node coupled to a first terminal of the capacitor; a receiver circuit, including a first input node coupled to a second terminal of the capacitor, and an output node coupled to the digital output signal; and a latching feedback circuit, including a first input node coupled to the output node of the receiver circuit, and an output node coupled to the second terminal of the capacitor to latch a toggled signal. An optional resistor can be inserted to increase the output resistance of the latching feedback circuit to be substantially larger than the output resistance of the driver circuit.

Abstract: A level shifter for level-shifting a digital input signal referenced to an input ground potential to a digital output signal referenced to an output ground potential, comprising: a capacitor; a driver circuit, including an input node coupled to the digital input signal, and an output node coupled to a first terminal of the capacitor; a receiver circuit, including a first input node coupled to a second terminal of the capacitor, and an output node coupled to the digital output signal; and a latching feedback circuit, including a first input node coupled to the output node of the receiver circuit, and an output node coupled to the second terminal of the capacitor to latch a toggled signal. An optional resistor can be inserted to increase the output resistance of the latching feedback circuit to be substantially larger than the output resistance of the driver circuit.

Abstract: An apparatus and methods to fabricate the apparatus for balancing a string of N series-connected electrical energy units (such as battery cells or modules) comprising: a transformer with a magnetic core and N windings; N switch circuits; N driver circuits, each driver circuit operable to turn ON/OFF a respective switch circuit in a charging or discharging or idling configuration; and a controller circuit.

Abstract: A driver for a power transistor switch comprising a FET complementary output stage which is driven by another FET complementary pre-driver stage which is further driven by an input-buffer and level-shifter stage. The pre-driver stage includes a current-limiting and cross-delaying circuit which is inserted in between drains terminals of a complementary FET pair. The current-limiting and cross-delaying circuit limits shoot-current at the pre-driver stage; and in conjunction with the FET pair and the input-buffer and level-shifter stage, it is adapted to delay turning on one complementary output FET until after the other complementary output FET is turned off, thereby preventing cross conduction at the output stage.

Abstract: A driver for a power transistor switch comprising a FET complementary output stage which is driven by another FET complementary pre-driver stage which is further driven by an input-buffer and level-shifter stage. The pre-driver stage includes a current-limiting and cross-delaying circuit which is inserted in between drains terminals of a complementary FET pair. The current-limiting and cross-delaying circuit limits shoot-current at the pre-driver stage; and in conjunction with the FET pair and the input-buffer and level-shifter stage, it is adapted to delay turning on one complementary output FET until after the other complementary output FET is turned off, thereby preventing cross conduction at the output stage.