Abstract: A system and method thereof to regulate a current to a capacitive load from a power supply connected to the capacitive load. The system includes a first switch between the power supply and the capacitive load, a super-capacitor configured for charging by the power supply and powering the capacitive load, a current limiting circuit between the super-capacitor and the power supply, a second switch between the super-capacitor and the capacitive load, and a power control circuit configured to control opening and closing of the first switch and the second switch independently, sense a voltage of the power supply, and sense a voltage of the super-capacitor.

Abstract: An apparatus, system, and method are disclosed for adjusting memory hold time. A detection module detects a hold time violation for a memory. An adjustment module increases a first voltage of a voltage controller in response to the hold time violation. The voltage controller supplies electrical current at the first voltage to a memory controller and at a reference voltage to the memory. The first and reference voltages are set independently.

Abstract: An apparatus, system, and method are disclosed for grounding IC outputs. A first switching module turns on when an IC power supply voltage exceeds a base voltage. The first switching module is in communication with IC outputs and a common ground. The IC outputs are configured to be pulled up to the IC power supply voltage through pull-up resistors when a first voltage is driven lower than the base voltage. In addition, the first switching module connects the IC outputs to the common ground. A second switching module turns on, turns turn off the first switching module, disconnects the IC outputs from the common ground, and pulls the IC outputs up to the IC power supply voltage when the IC power supply voltage exceeds a minimum working voltage.

Abstract: An apparatus, system, and method are disclosed for adjusting memory hold time. A detection module detects a hold time violation for a memory. An adjustment module increases a first voltage of a voltage controller in response to the hold time violation. The voltage controller supplies electrical current at the first voltage to a memory controller and at a reference voltage to the memory. The first and reference voltages are set independently.

Abstract: A storage device comprises a storage device controller, a storage space, and a storage interface coupled to at least one computer system. The storage space is partitioned into a single or a plurality of regions, at least one of which is configurable to be associated with a protected access mode (read and/or write protect mode) through a configuration program (preferably password-protected). Whenever the storage device receives a data access request from a computer system, the storage device controller rejects the request if it determines that a portion or the entirety of a logical address range of the requested data block locates in a region associated with a protected access mode prohibiting the request. A region associated with a read-and-write-protect mode is a data safe box, wherein confidential and/or private and/or valuable data can be stored and protected against any accidental or malicious disclosure or tampering by a malicious program or an intruder.

Abstract: An electrostatic protection network is disclosed that may be employed in a disk drive having a magneto-resistive read element. The network comprises a ground; and an array that block a signal current flow between the read element and the ground while a signal voltage is below a predetermined value and conducts the signal current from the read element to the ground while the signal voltage is above the predetermined value. The array is formed of a N-channel and P-channel junction field effect transistors. Thus, electrostatic discharge events are dissipated through the network to diminish damage to the read element during an ESD event.

Abstract: An n-bit analog to digital, (A/D), converter utilizes n comparators, and n internal digital to analog, (D/A) converters. The n D/A converters have the same full-scale output, and the same absolute accuracy in terms of voltage or current, but have n different resolutions ranging consecutively from a 1-bit D/A converter to an n-bit D/A converter. The n-bit A/D converter is divisible into n stages, ranging consecutively from a first stage containing the 1-bit D/A converter and a first comparator, to an n-th stage containing the n-bit D/A converter and an n-th comparator. The least significant bit input terminal of each D/A converter is connected to a logic high level. In each stage, an analog input signal is compared with a reference provided by a D/A converter.