Abstract: Implementations of the present application provide a semiconductor device, a fabrication method and a memory system. The semiconductor device includes a plurality of semiconductor pillars arranged in an array and a word line structure. The plurality of semiconductor pillars extend along a first direction and include at least one side face, wherein the plurality of semiconductor pillars are arranged in rows along a second direction perpendicular to the first direction. The word line structure is located between a first row and a second row of semiconductor pillars that are adjacent, and includes a first word line structure and a second word line structure spaced apart from the first word line structure, wherein the first word line structure is connected with a side face of the first row of semiconductor pillars, and the second word line structure is connected with a side face of the second row of semiconductor pillars.

Abstract: Example three-dimensional (3D) memory devices, methods, and memory systems for connecting vertical transistors and capacitors using connect structures are disclosed. One example method includes forming a first structure that includes multiple vertical transistors. A connect layer is formed over the first structure. The connect layer is etched to form connect structures, where each of the connect structures is coupled to a corresponding one of the vertical transistors. Multiple capacitors are formed over the connect layer, where each of the plurality of capacitors is coupled to a respective connect structure.

Abstract: In certain aspects, a three-dimensional (3D) memory device includes a second semiconductor structure. The second semiconductor structure includes an array of memory cells, each of the memory cells including a vertical transistor extending in a first direction, and a storage unit coupled to the vertical transistor, a plurality of bit lines coupled to the memory cells and each extending in a second direction perpendicular to the first direction, and a plurality of word lines coupled to the memory cells and each extending in a third direction perpendicular to the first direction and the second direction. The vertical transistor includes a semiconductor body extending in the first direction, and a gate structure in contact with one side of the semiconductor body in the second direction. A respective one of the bit lines and a respective storage unit are coupled to opposite ends of each one of the memory cells in the first direction.

Abstract: A semiconductor structure and a method for forming the semiconductor structure are provided. The semiconductor structure includes: a substrate including active areas and isolation regions; a plurality of first recesses disposed in the substrate; a first word line gate structure, a second word line gate structure, a first connection gate and a second connection gate disposed on side surfaces of a first recess; a dielectric layer disposed in the first recess; a second recess and a third recess disposed in the dielectric layer in the isolation regions, central axes of the third recess and the second recess doing not overlap along the second direction; a first isolation structure disposed in the second recess; a second isolation structure disposed in the third recess; a first connection plate disposed on the second connection gate; and a second connection plate disposed on the first connection gate.

Abstract: A memory device includes a substrate, a stack over the substrate, and a gate line slit extending along a first direction and dividing the stack into two portions. The stack includes a connection portion that connects the two portions of the stack. The connection portion includes at least two sub-connection portions along a second direction perpendicular to the first direction. The gate line slit includes at least two portions along the first direction. Each sub-connection portion is between adjacent two portions of the gate line slit.

Abstract: Systems, devices, and methods for managing three-dimensional semiconductor devices are provided. In one aspect, a method includes: forming strings of memory cells in a first side of a semiconductor substrate having a semiconductor material, forming alternating stripes of the semiconductor material and an isolating material in a second, opposite side of the semiconductor substrate, and forming bit lines in the second side of the semiconductor substrate. The bit lines can be formed by depositing a layer of a metallic material on the alternating stripes of the semiconductor material and the isolating material, and forming each bit line of the bit lines in a corresponding stripe of the semiconductor material of the alternating stripes by forming a composite conductive material based on the metallic material and the semiconductor material in the corresponding stripe of the semiconductor material.

Abstract: Disclosed are a semiconductor structure and a manufacturing method which includes providing a substrate; forming a first recessed area from a first surface of the substrate, wherein at least two protruding structures are reserved in the first recessed area, and there are at least some of non-overlapping areas in the projections of any two adjacent protruding structures in the direction perpendicular to the extending direction of the protruding structures; filling the first recessed area with an insulating material; thinning from a second surface of the substrate until the insulating material is exposed to the second surface protruding structures from the second surface to form a second recessed area; filling the second recessed area with a conductive material to form bit lines; and at surface positions of the bit lines corresponding to the non-overlapping areas, forming bit line lead-out structures.

Abstract: The present application discloses a patterning method, a semiconductor structure and a memory. The patterning method includes: after forming a mandrel structure in a mask layer on a side of a to-be-etched layer, removing part of the mandrel structure to form a first trench with a smaller length and a second trench with a larger length, and forming a first mask pattern and a second mask pattern through the first trench and the second trench so as to form a first patterned structure and a second patterned structure of different lengths. The present application can improve the applicability of the patterning method, and reduce the process difficulty and cost of fine patterning for forming patterns of different sizes, such that the patterning method provided by the present application can meet more process requirements.

Abstract: Embodiments of the disclosure provide a method for manufacturing a memory device, the method includes operations. At least one cell block is formed on a wafer, each of the at least one cell block includes multiple memory cells distributed in an array, each of the multiple memory cells includes a transistor and a storage capacitor connected to a source of the transistor. Bit lines are formed on the wafer, and each of the bit lines is connected to a drain of the transistor, here each of the bit lines and the storage capacitor are located on opposite surfaces of the wafer in a thickness direction respectively. A peripheral circuit is formed above the bit lines on the wafer along a perpendicular of the wafer, here the peripheral circuit includes at least a Sensing Amplifier (SA). An electrical connection is formed between the bit line and the SA.

Abstract: In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, and a first bonding interface between the first semiconductor structure and the second semiconductor structure. The first semiconductor structure includes a peripheral circuit. The second semiconductor structure includes an array of memory cells and a plurality of bit lines coupled to the memory cells and each extending in a second direction perpendicular to the first direction. Each of the memory cells includes a vertical transistor extending in a first direction, and a storage unit coupled to the vertical transistor. A respective one of the bit lines and a respective storage unit are coupled to opposite ends of each one of the memory cells in the first direction. The array of memory cells is coupled to the peripheral circuit across the first bonding interface.

Abstract: The present application discloses a semiconductor device and a fabrication method thereof, and a memory system. The device includes a plurality of semiconductor pillars extending in a third direction, and a plurality of gate structures and shielding structures extending along a first direction. The gate structures and the shielding structures are in a staggered distribution along a second direction, and the semiconductor pillars are located between the shielding structures and the gate structures that are adjacent. Sizes of the gate structures along the first direction are smaller than sizes of the shielding structures along the first direction, and orthographic projections of the gate structures are within ranges of orthographic projections of the shielding structures along the second direction.

Abstract: In certain aspects, a memory device includes a semiconductor layer, a peripheral circuit including a peripheral transistor in contact with the semiconductor layer, an array of memory cells disposed beside the semiconductor layer and the peripheral circuit, and bit lines coupled to the memory cells. Each of the memory cells includes a vertical transistor extending in a first direction, and a storage unit coupled to the vertical transistor. Each of the bit lines extends in a second direction perpendicular to the first direction. A respective one of the bit lines and a respective storage unit are coupled to opposite ends of each one of the memory cells in the first direction.

Abstract: Examples include forming first trenches extending along a first direction on a first side of a semiconductor layer, and forming an insulation layer within the first trenches; forming second trenches extending along a second direction on the first side, the depths of the second trenches less than depths of the first trenches, the first and second directions intersecting; forming a first gate insulation layer and first gate conductive layer sequentially on inner walls of the second trenches; removing part of the semiconductor layer, part of the insulation layer and part of the first gate insulation layer from a second side of the semiconductor layer facing away from the first side, to expose the first gate conductive layer; and removing a part of the first gate conductive layer from the second side, to divide the first gate conductive layer into first gates located on opposite sidewalls of the second trenches respectively.

Abstract: Examples of the present application provide a semiconductor device, a memory system and a fabrication method of a semiconductor device. The semiconductor device includes: a silicon contact structure; a metal silicide layer on one side of the silicon contact structure; a bit line structure located on the side of the metal silicide layer away from the silicon contact structure and extending in a first direction; and a sidewall structure covering the opposite sides of the bit line structure and the opposite sides of the metal silicide layer in the first direction and extending further to cover the opposite sides, in the first direction, of the first end of the silicon contact structure proximate to the metal silicide layer.

Abstract: A semiconductor structure and a manufacturing method include providing a substrate with a first surface and a second surface, which are opposite each other; from the first surface of the substrate, forming a transistor array having a plurality of transistors; thinning the substrate from the second surface until a first end of a conductive channel of each transistor is exposed, wherein the first end is the end of the conductive channel that is close to the second surface; forming an insulating layer, which covers at least part of the first end of the conductive channel, such that a first width of the exposed first end of the conductive channel is less than a second width of the conductive channel; and forming a bit line structure, which covers the exposed part of the first end of the conductive channel.

Abstract: A semiconductor structure and a method for preparing the same are provided. The semiconductor structure includes: a substrate having a plurality of active regions that are arrayed. Each of the plurality of active regions includes an active portion and an active extension portion. A word line gate structure is positioned in the substrate. The word line gate structure runs through the plurality of active regions. The word line gate structure includes a word line layer and a word line isolation layer. The active extension portion covers a surface of the active portion and is at least partially positioned on the word line gate structure. A word line isolation extension portion is positioned in the active extension portion, where the word line isolation extension portion is connected to the word line isolation layer and formed on a surface of the word line isolation layer.

Abstract: A semiconductor structure and a formation method therefor. The semiconductor structure comprises: a substrate, which has opposite first and second surfaces, and comprises several discrete active areas arranged in a first direction and parallel to a second direction, wherein the first direction is perpendicular to the second direction; word line gate structures, which are disposed in the active areas, extend from the first surface to the second surface, are arranged in the second direction, and run through the active areas along the first direction; a first isolation structure, which is disposed in the substrate and extends from the second surface to the first surface; bit line structures, which are disposed on the first surface, electrically coupled with the active areas, arranged in the first direction, and parallel to the second direction; and capacitor structures, which are disposed on the second surface and electrically coupled with the active areas.

Abstract: Embodiments of staircase structures of a three-dimensional memory device and fabrication method thereof are disclosed. The semiconductor structure includes a first and a second film stacks, wherein the first film stack is disposed over the second film stack and has M1 number of layers. The second film stack has M2 number of layers. M1 and M2 are whole numbers. The semiconductor structure also includes an upper staircase structure and a lower staircase structure, wherein the upper staircase structure is formed in the first film stack and the lower staircase structure is formed in the second film stack. The upper and lower staircase structures are next to each other with an offset.

Abstract: A dynamic random access memory and a forming method therefor. The dynamic random access memory comprises: a substrate (100), which has opposite first surface (101) and second surface (102), and comprises several active regions (103), and each active region (103) comprises an isolation region (104), a channel region (105) and a word line region (106); a first isolation layer (108), which is located in the isolation region (104); a word line gate structure (111), which is located in the word line region (106); a first source/drain dope region (112), which is located in the channel region (105) on the first surface (101); a bit line layer (114) which is located on the first surface (101); a second source/drain dope region (116) which is located in the channel region (105) on the second surface (102); and several capacitor structures (119), which are located on the second surface (102).

Abstract: A three-dimensional (3D) memory device includes a plurality of channel structures extending along a vertical direction, a first staircase structure including a plurality of division block structures arranged along a first direction on a side of the channel structures, and a top select gate staircase structure disposed between the channel structures and the first staircase structure in a second direction that is different from the first direction. At least one of the division block structures includes a plurality of staircases arranged along the second direction. At least one of the staircases includes a plurality of steps arranged along the first direction.