Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate and a memory stack including interleaved conductive layers and dielectric layers above the substrate. The 3D memory device also includes a slit structure extending vertically through the memory stack and extending laterally along a serpentine path to separate the memory stack into a first area and a second area. The 3D memory device further includes first channel structures each extending vertically through the first area of the memory stack and including a drain at its upper end, and second channel structures each extending vertically through the second area of the memory stack and including a source at its upper end. The 3D memory device further includes semiconductor connections disposed vertically between the substrate and the memory stack.

Abstract: Embodiments of staircase structures of a three-dimensional memory device and fabrication method thereof are disclosed. The semiconductor structure includes a first and a second film stacks, wherein the first film stack is disposed over the second film stack and has M1 number of layers. The second film stack has M2 number of layers. M1 and M2 are whole numbers. The semiconductor structure also includes a first and a second staircase structures, wherein the first staircase structure is formed in the first film stack and the second staircase structure is formed in the second film stack. The first and second staircase structures are next to each other with an offset.

Abstract: Three-dimensional (3D) memory devices and methods for forming the 3D memory devices are provided. In one example, a 3D memory device includes a substrate, a memory stack including interleaved conductive layers and dielectric layers on the substrate, and a staircase structure on one side of the memory stack. The 3D memory device also includes a staircase contact in the staircase structure and a plurality of dummy source structures each extending vertically through the staircase structure. The plurality of dummy source structures surround the staircase contact.

Abstract: Embodiments of a three-dimensional (3D) memory device are provided. The 3D memory device includes a substrate, a memory stack with interleaved conductive layers and dielectric layers over the substrate, an array of channel structures each extending vertically through the memory stack, and a plurality of contact hole structures each extending vertically through the memory stack and electrically connected to a common source of one or more of the channel structures. At least one of the plurality of contact hole structures is surrounded by a plurality of the channel structures of nominally equal lateral distances to the respective contact hole structure.

Abstract: The present disclosure provides a three-dimensional (3D) memory device and a method for forming the same. The 3D memory device can comprise a channel structure region including a plurality of channel structures; a first staircase structure in a first staircase region including a plurality of division block structures arranged along a first direction on a first side of the channel structure, and a second staircase structure in a second staircase region including a plurality of division block structures arranged along the first direction on a second side of the channel structure. A first vertical offset defines a boundary between adjacent division block structures. Each division block structure includes a plurality of staircases arranged along a second direction that is different from the first direction. Each staircase includes a plurality of steps arranged along the first direction.

Abstract: Methods and structures of a three-dimensional memory device are disclosed. In an example, the method comprises: providing a substrate; forming an alternating stack over the substrate, the alternating stack comprising a plurality of tiers of sacrificial layer/insulating layer pairs extending along a first direction substantially parallel to a top surface of the substrate; forming a plurality of tiers of word lines extending along the first direction based on the alternating stack; forming at least one connection portion conductively connecting two or more of the word lines of the plurality of tiers of word lines; and forming at least one metal contact via conductively shared by connected word lines, the at least one metal contact via being connected to at least one metal interconnect.

Abstract: Embodiments of methods for forming a staircase structure of a three-dimensional (3D) memory device are disclosed. In an example, a first plurality of stairs of the staircase structure are formed based on a first photoresist mask. Each of the first plurality of stairs includes a number of divisions at different depths. After forming the first plurality of stairs, a second plurality of stairs of the staircase structure are formed based on a second photoresist mask. Each of the second plurality of stairs includes the number of divisions. The staircase structure tilts downward and away from a memory array structure of the 3D memory device from the first plurality of stairs to the second plurality of stairs.

Abstract: Embodiments of 3D memory devices having zigzag slit structures and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a memory stack including interleaved conductive layers and dielectric layers above the substrate, an array of memory strings each extending vertically through the memory stack, and a plurality of slit structures laterally dividing the array of memory strings into a plurality of memory regions. Each of the plurality of slit structures extends vertically through the memory stack and extends laterally in a first zigzag pattern in a plan view.

Abstract: Methods and structures of a three-dimensional memory device are disclosed. In an example, the memory device includes a substrate, a first tier of conductor layers of a first length comprising a first plurality of conductor layers extending along a first direction over the substrate. The first direction is substantially parallel to a top surface of the substrate. In some embodiments, the memory device also includes at least one connection portion conductively connecting two or more conductor layers of the first tier, and a first metal contact via conductively shared by connected conductor layers of the first tier and connected to a first metal interconnect.

Abstract: Embodiments of methods for forming a staircase structure of a three-dimensional (3D) memory device are disclosed. In an example, a first plurality of stairs of the staircase structure are formed based on a first photoresist mask. Each of the first plurality of stairs includes a number of divisions at different depths. After forming the first plurality of stairs, a second plurality of stairs of the staircase structure are formed based on a second photoresist mask. Each of the second plurality of stairs includes the number of divisions. The staircase structure tilts downward and away from a memory array structure of the 3D memory device from the first plurality of stairs to the second plurality of stairs.

Abstract: Embodiments of 3D memory devices having zigzag slit structures and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a memory stack including interleaved conductive layers and dielectric layers above the substrate, an array of memory strings each extending vertically through the memory stack, and a plurality of slit structures laterally dividing the array of memory strings into a plurality of memory regions. Each of the plurality of slit structures extends vertically through the memory stack and extends laterally in a first zigzag pattern in a plan view.

Abstract: Embodiments of 3D memory devices with a dielectric etch stop layer and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a dielectric etch stop layer disposed on the substrate, a memory stack disposed on the dielectric etch stop layer and including a plurality of interleaved conductor layers and dielectric layers, and a plurality of memory strings each extending vertically through the memory stack and including a selective epitaxial growth (SEG) plug in a bottom portion of the memory string. The SEG plug is disposed on the substrate.

Abstract: Methods and structures of a three-dimensional memory device are disclosed. In an example, the memory device includes a substrate, a first tier of conductor layers of a first length comprising a first plurality of conductor layers extending along a first direction over the substrate. The first direction is substantially parallel to a top surface of the substrate. In some embodiments, the memory device also includes at least one connection portion conductively connecting two or more conductor layers of the first tier, and a first metal contact via conductively shared by connected conductor layers of the first tier and connected to a first metal interconnect.

Abstract: The present disclosure describes methods and structures for three-dimensional memory devices. The methods include providing a bottom substrate and forming a plurality of doped layers over the bottom substrate. The plurality of doped layers has a total thickness in a thickness range such that a top surface of the plurality of doped layers is substantially flat and a doping concentration of each of the plurality of doped layers is substantially uniform along a direction substantially perpendicular to the top surface of the plurality of doped layers.