Patents by Inventor Wenyu HUA

Wenyu HUA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240244833
    Abstract: A dynamic random access memory and a forming method therefor. The dynamic random access memory comprises: a substrate (100), which has opposite first surface (101) and second surface (102), and comprises several active regions (103), and each active region (103) comprises an isolation region (104), a channel region (105) and a word line region (106); a first isolation layer (108), which is located in the isolation region (104); a word line gate structure (111), which is located in the word line region (106); a first source/drain dope region (112), which is located in the channel region (105) on the first surface (101); a bit line layer (114) which is located on the first surface (101); a second source/drain dope region (116) which is located in the channel region (105) on the second surface (102); and several capacitor structures (119), which are located on the second surface (102).
    Type: Application
    Filed: September 2, 2021
    Publication date: July 18, 2024
    Applicant: ICLEAGUE TECHNOLOGY CO., LTD.
    Inventors: Wenyu HUA, Xing YU
  • Publication number: 20240224526
    Abstract: A three-dimensional (3D) memory device includes a plurality of channel structures extending along a vertical direction, a first staircase structure including a plurality of division block structures arranged along a first direction on a side of the channel structures, and a top select gate staircase structure disposed between the channel structures and the first staircase structure in a second direction that is different from the first direction. At least one of the division block structures includes a plurality of staircases arranged along the second direction. At least one of the staircases includes a plurality of steps arranged along the first direction.
    Type: Application
    Filed: March 18, 2024
    Publication date: July 4, 2024
    Inventors: Zhong ZHANG, Wenyu HUA, Zhiliang XIA
  • Publication number: 20240206147
    Abstract: A semiconductor structure and method for manufacturing thereof are provided. The semiconductor structure includes a vertical transistor. The vertical transistor includes a semiconductor body extending in a first direction. The semiconductor body includes a source/drain at one end of the semiconductor body. The vertical transistor also includes a gate structure coupled to at least one side of the semiconductor body. The gate structure includes a gate dielectric and a gate electrode. The vertical transistor further includes a silicide. At least part of the silicide is above the source/drain. An area of the silicide is larger than an area of a first surface of the source/drain. The first surface is vertical to the first direction.
    Type: Application
    Filed: June 26, 2023
    Publication date: June 20, 2024
    Inventors: Hao Zhang, Bingjie Yan, Ya Wang, Wenyu Hua
  • Publication number: 20240196588
    Abstract: A semiconductor structure and a method for forming the semiconductor structure are provided. The semiconductor structure includes: a substrate including a first surface and a second surface, which includes a plurality of active areas arranged along a first direction and in parallel along a second direction; a plurality of first recesses arranged in the substrate; a word line gate structure disposed in a first recess, which includes a first side wall and a second side wall, wherein the second side wall is adjacent to an active area; a first isolation structure disposed in the first recess and disposed between the word line gate structure and an active area; a plurality of capacitor structures disposed on the first surface and electrically coupled with an active area; and a plurality of bit lines disposed on the second surface, which are arranged along the first direction and parallel to the second direction.
    Type: Application
    Filed: August 30, 2021
    Publication date: June 13, 2024
    Applicant: ICLEAGUE TECHNOLOGY CO., LTD.
    Inventors: Wenyu HUA, Boyong HE
  • Publication number: 20240188276
    Abstract: Embodiments of the disclosure provide a method for manufacturing a memory device, the method includes operations. At least one cell block is formed on a wafer, each of the at least one cell block includes multiple memory cells distributed in an array, each of the multiple memory cells includes a transistor and a storage capacitor connected to a source of the transistor. Bit lines are formed on the wafer, and each of the bit lines is connected to a drain of the transistor, here each of the bit lines and the storage capacitor are located on opposite surfaces of the wafer in a thickness direction respectively. A peripheral circuit is formed above the bit lines on the wafer along a perpendicular of the wafer, here the peripheral circuit includes at least a Sensing Amplifier (SA). An electrical connection is formed between the bit line and the SA.
    Type: Application
    Filed: August 6, 2021
    Publication date: June 6, 2024
    Applicant: ICLEAGUE TECHNOLOGY CO., LTD.
    Inventors: Wenyu HUA, Fandong LIU, Xiao DING
  • Publication number: 20240186319
    Abstract: The disclosure provides a transistor array and a method for manufacturing the same, and a semiconductor device and a method for manufacturing the same. The method for manufacturing a transistor array may include the following operations. A wafer is provided. The wafer is partially etched from a first surface of the wafer along a first direction, to form a grid-like etched trench and a transistor pillar array, here the transistor pillar array includes multiple transistor pillars arranged in an array, each of the multiple transistor pillars is located at a corresponding grid point of the grid-like etched trench and has a first preset thickness smaller than an initial thickness of the wafer; and the first direction is a thickness direction of the wafer and is perpendicular to the first surface. An insulating material is deposited in the grid-like etched trench to form an insulating layer.
    Type: Application
    Filed: August 6, 2021
    Publication date: June 6, 2024
    Applicant: ICLEAGUE TECHNOLOGY CO., LTD.
    Inventors: Wenyu HUA, Zhongwei LUO, Zhi ZHANG
  • Publication number: 20240179922
    Abstract: Embodiments provide a transistor and a method for manufacturing same, a semiconductor device and a method for manufacturing same. The method for manufacturing a transistor includes operations. A wafer is provided, the wafer has multiple transistor formation regions, each of which has a transistor pillar with an exposed gate formation surface. A gate oxide layer and a gate are sequentially formed on the gate formation surface of each of the transistor pillars. A source is formed at a first end of each of the transistor pillars. A drain is formed at a second end of each of the transistor pillars, here the first end and the second end are opposite ends of each of the transistor pillars in a first direction which is a thickness direction of the wafer; a part of each of the transistor pillars between the source and the drain forms a channel region of the transistor.
    Type: Application
    Filed: August 6, 2021
    Publication date: May 30, 2024
    Applicant: ICLEAGUE TECHNOLOGY CO., LTD.
    Inventors: Wenyu HUA, Xilong WANG
  • Publication number: 20240172411
    Abstract: The disclosure provides a transistor array and a method for manufacturing the same, and a semiconductor device and a method for manufacturing the same. The method for manufacturing a transistor array may include the following operations. A wafer is provided. The wafer is partially etched from a first surface of the wafer along a first direction, to form a grid-like etched trench and a transistor pillar array, here the transistor pillar array includes multiple transistor pillars arranged in an array, each of the multiple transistor pillars has a first preset thickness smaller than an initial thickness of the wafer. An insulating material is deposited in the grid-like etched trench to form an insulating layer surrounding each of the multiple transistor pillars. The insulating layer is etched to expose a first sidewall and a second sidewall, opposite to each other in a second direction, of each of the multiple transistor pillars.
    Type: Application
    Filed: August 6, 2021
    Publication date: May 23, 2024
    Applicant: ICLEAGUE TECHNOLOGY CO., LTD.
    Inventors: Wenyu HUA, Zhongwei LUO, Zhi ZHANG
  • Publication number: 20240172415
    Abstract: In certain aspects, a semiconductor device includes a vertical transistor, a metal bit line, and a pad layer. The vertical transistor includes a semiconductor body extending in a first direction, and a gate structure coupled to at least one side of the semiconductor body. The gate structure includes a gate dielectric and a gate electrode. The metal bit line extends in a second direction perpendicular to the first direction and coupled to a terminal of the vertical transistor via an ohmic contact. The pad layer is positioned between the gate electrode and the metal bit line in the first direction. The gate dielectric and the pad layer have different dielectric materials.
    Type: Application
    Filed: December 30, 2022
    Publication date: May 23, 2024
    Inventors: Hongbin ZHU, Weihua CHENG, Wei LIU, Wenyu HUA, Bingjie YAN, Zichen LIU
  • Publication number: 20240172418
    Abstract: A semiconductor structure and a forming method therefor. The forming method comprises: providing a first substrate, which has opposite first and second faces, and comprises several discrete active regions arranged in a first direction and parallel to a second direction that is perpendicular to the first direction, wherein the first face exposes an isolation layer disposed between adjacent active regions; forming in the first substrate several first recesses, which extend from the first face to the second face, are arranged in the second direction, and penetrates the active regions in the first direction, and have a bottom with a distance less than the thickness of the isolation layer from the first face; forming word line gate structures within the first recesses; thinning the first substrate from the second face; and forming on the second face bit lines, wherein one active region and one bit line are electrically interconnected.
    Type: Application
    Filed: January 10, 2022
    Publication date: May 23, 2024
    Applicant: ICLEAGUE TECHNOLOGY CO., LTD.
    Inventors: Wenyu HUA, Boyong HE
  • Patent number: 11974431
    Abstract: The present disclosure provides a method for forming a three-dimensional memory device. The method can comprise forming a film stack with a plurality of dielectric layer pairs on a substrate, forming a channel structure region in the film stack including a plurality of channel structures, and forming a first staircase structure in a first staircase region and a second staircase structure in a second staircase region. Each of the first staircase structure and the second staircase structure can include a plurality of division block structures arranged along a first direction. A first vertical offset defines a boundary between adjacent division block structures. Each division block structure includes a plurality of staircases arranged along a second direction that is different from the first direction. Each staircase includes a plurality of steps arranged along the first direction.
    Type: Grant
    Filed: June 21, 2021
    Date of Patent: April 30, 2024
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Zhong Zhang, Wenyu Hua, Zhiliang Xia
  • Publication number: 20240038856
    Abstract: A semiconductor device includes a first vertically-oriented semiconductor pillar having one or more sidewalls, and a top surface, the first vertically-oriented semiconductor pillar having a first width, a first dielectric material abutted to the one or more sidewalls of the first vertically-oriented semiconductor pillar, and a first conductive structure having a first surface, and having a second width that is greater than the first width, the first conductive structure disposed such that a second portion of its first surface is in electrical contact with the top surface of the first vertically-oriented semiconductor pillar, wherein a first portion of the first surface of the first conductive structure extends laterally beyond the top surface of the first vertically-oriented semiconductor pillar, and the second portion of the first surface is disposed on the first dielectric material.
    Type: Application
    Filed: July 24, 2023
    Publication date: February 1, 2024
    Inventors: Wenxiang Xu, Fandong Liu, Wenyu Hua, Ya Wang, Dongmen Song
  • Publication number: 20230413560
    Abstract: A memory device includes a substrate, a stack over the substrate, and a gate line slit extending along a first direction and dividing the stack into two portions. The stack includes a connection portion that connects the two portions of the stack. The connection portion includes at least two sub-connection portions along a second direction perpendicular to the first direction. The gate line slit includes at least two portions along the first direction. Each sub-connection portion is between adjacent two portions of the gate line slit.
    Type: Application
    Filed: August 22, 2023
    Publication date: December 21, 2023
    Inventors: Qiang Xu, Fandong Liu, Zongliang Huo, Zhiliang Xia, Yaohua Yang, Peizhen Hong, Wenyu Hua, Jia He
  • Publication number: 20230397412
    Abstract: A memory device includes a memory cell and a peripheral circuit. The memory cell includes a vertical transistor having a first terminal and a second terminal, a storage unit having a first end coupled to the first terminal of the vertical transistor, and a bit line coupled to the second terminal of the vertical transistor. The peripheral circuit is coupled to the bit line. The vertical transistor includes a semiconductor body extending in a first direction, and a gate structure coupled to at least one side of the semiconductor body. The bit line is disposed between the vertical transistor and the peripheral circuit along the first direction.
    Type: Application
    Filed: June 2, 2023
    Publication date: December 7, 2023
    Inventors: Wei Liu, Hongbin Zhu, Wenyu Hua
  • Publication number: 20230380137
    Abstract: A semiconductor device and methods for forming the same are provided. The semiconductor device includes an array of vertical transistors. Each transistor includes a semiconductor body extending in a vertical direction, and a gate structure located adjacent to a sidewall of the semiconductor body. The gate structures of each row of vertical transistors are connected with each other and extend along a first lateral direction to form a word line. A first word line of a first row of vertical transistors is located at a first side of the semiconductor bodies of the first row of vertical transistors along a second lateral direction perpendicular to the first lateral direction; and a second word line of a second row of vertical transistors adjacent to the first row of vertical transistors is located at a second side of the semiconductor bodies of the second row of vertical transistors along the second lateral direction.
    Type: Application
    Filed: July 17, 2023
    Publication date: November 23, 2023
    Inventors: Wei Liu, Hongbin Zhu, Yanhong Wang, Bingjie Yan, Wenyu Hua, Fandong Liu, Ya Wang
  • Patent number: 11792989
    Abstract: Methods and structures of a three-dimensional memory device are disclosed. In an example, the memory device comprises a substrate, a stack structure on the substrate, and at least one gate line slit extending along a first direction substantially parallel to a top surface of the substrate, and dividing the stack structure into at least two portions. The stack structure includes at least one connection portion that divides the at least one gate line slit, and conductively connects the at least two portions.
    Type: Grant
    Filed: October 25, 2021
    Date of Patent: October 17, 2023
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Qiang Xu, Fandong Liu, Zongliang Huo, Zhiliang Xia, Yaohua Yang, Peizhen Hong, Wenyu Hua, Jia He
  • Publication number: 20230064388
    Abstract: In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, and a bonding interface between the first semiconductor structure and the second semiconductor structure. The first semiconductor structure includes a peripheral circuit. The second semiconductor structure includes an array of memory cells and a plurality of bit lines coupled to the memory cells and each extending in a second direction perpendicular to the first direction. Each of the memory cells includes a vertical transistor extending in a first direction, and a storage unit coupled to the vertical transistor. A respective one of the bit lines and a respective storage unit are coupled to opposite ends of each one of the memory cells in the first direction. Two adjacent vertical transistors of the vertical transistors in the second direction are mirror-symmetric to one another. The array of memory cells is coupled to the peripheral circuit across the bonding interface.
    Type: Application
    Filed: December 16, 2021
    Publication date: March 2, 2023
    Inventors: Wei Liu, Hongbin Zhu, Ziqun Hua, Ning Jiang, Wenyu Hua
  • Publication number: 20230062524
    Abstract: In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, and a first bonding interface between the first semiconductor structure and the second semiconductor structure. The first semiconductor structure includes a peripheral circuit. The second semiconductor structure includes an array of memory cells and a plurality of bit lines coupled to the memory cells and each extending in a second direction perpendicular to the first direction. Each of the memory cells includes a vertical transistor extending in a first direction, and a storage unit coupled to the vertical transistor. A respective one of the bit lines and a respective storage unit are coupled to opposite ends of each one of the memory cells in the first direction. The array of memory cells is coupled to the peripheral circuit across the first bonding interface.
    Type: Application
    Filed: December 16, 2021
    Publication date: March 2, 2023
    Inventors: Wei Liu, Hongbin Zhu, Ziqun Hua, Ning Jiang, Wenyu Hua
  • Publication number: 20230069096
    Abstract: In certain aspects, a memory device includes a semiconductor layer, a peripheral circuit including a peripheral transistor in contact with the semiconductor layer, an array of memory cells disposed beside the semiconductor layer and the peripheral circuit, and bit lines coupled to the memory cells. Each of the memory cells includes a vertical transistor extending in a first direction, and a storage unit coupled to the vertical transistor. Each of the bit lines extends in a second direction perpendicular to the first direction. A respective one of the bit lines and a respective storage unit are coupled to opposite ends of each one of the memory cells in the first direction.
    Type: Application
    Filed: December 16, 2021
    Publication date: March 2, 2023
    Inventors: Simon Shi-Ning Yang, Hongbin Zhu, Wei Liu, Wenyu Hua
  • Patent number: 11462558
    Abstract: Embodiments of staircase structures of a three-dimensional memory device and fabrication method thereof are disclosed. The semiconductor structure includes a first and a second film stacks, wherein the first film stack is disposed over the second film stack and has M1 number of layers. The second film stack has M2 number of layers. M1 and M2 are whole numbers. The semiconductor structure also includes a first and a second staircase structures, wherein the first staircase structure is formed in the first film stack and the second staircase structure is formed in the second film stack. The first and second staircase structures are next to each other with an offset.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: October 4, 2022
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Zhong Zhang, Wenyu Hua, Bo Huang, Zhiliang Xia