Patents by Inventor Werner Pamler
Werner Pamler has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8877631Abstract: An interconnect arrangement and fabrication method are described. The interconnect arrangement includes an electrically conductive mount substrate, a dielectric layer formed on the mount substrate, and an electrically conductive interconnect formed on the dielectric layer. At least a portion of the dielectric layer under the interconnect contains a cavity. To fabricate the interconnect arrangement, a sacrificial layer is formed on the mount substrate and the interconnect layer is formed on the sacrificial layer. The interconnect layer and the sacrificial layer are structured to produce a structured interconnect on the structured sacrificial layer. A porous dielectric layer is formed on a surface of the mount substrate and of the structured interconnect as well as the sacrificial layer. The sacrificial layer is then removed to form the cavity under the interconnect.Type: GrantFiled: May 18, 2011Date of Patent: November 4, 2014Assignee: Infineon Technologies AGInventors: Manfred Engelhardt, Werner Pamler, Guenther Schindler
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Publication number: 20110217839Abstract: An interconnect arrangement and fabrication method are described. The interconnect arrangement includes an electrically conductive mount substrate, a dielectric layer formed on the mount substrate, and an electrically conductive interconnect formed on the dielectric layer. At least a portion of the dielectric layer under the interconnect contains a cavity. To fabricate the interconnect arrangement, a sacrificial layer is formed on the mount substrate and the interconnect layer is formed on the sacrificial layer. The interconnect layer and the sacrificial layer are structured to produce a structured interconnect on the structured sacrificial layer. A porous dielectric layer is formed on a surface of the mount substrate and of the structured interconnect as well as the sacrificial layer. The sacrificial layer is then removed to form the cavity under the interconnect.Type: ApplicationFiled: May 18, 2011Publication date: September 8, 2011Inventors: Manfred ENGELHARDT, Werner PAMLER, Guenther SCHINDLER
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Patent number: 7807563Abstract: In a method for manufacturing a layer arrangement, a plurality of electrically conductive structures are embedded in a substrate. Material of the substrate is removed at least between adjacent electrically conductive structures. An interlayer is formed on at least one portion of sidewalls of each of the electrically conductive structures. A first layer is formed on the interlayer where an upper partial region of the interlayer remaining free of a covering with the first layer. An electrically insulating second layer is formed selectively on that partial region of the interlayer which is free of the first layer, in such a way that the electrically insulating second layer bridges adjacent electrically conductive structures such that air gaps are formed between adjacent electrically conductive structures.Type: GrantFiled: April 12, 2007Date of Patent: October 5, 2010Assignee: Infineon Technologies AGInventors: Zvonimir Gabric, Werner Pamler, Guenther Schindler, Gernot Steinlesberger, Andreas Stich, Martin Traving, Eugen Unger
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Patent number: 7755160Abstract: A method for producing a layer arrangement is disclosed. A layer of oxygen material and nitrogen material is formed over a substrate that has a plurality of electrically conductive structures and/or over a part of a surface of the electrically conductive structures. The layer is formed using a plasma-enhanced chemical vapor deposition process with nitrogen material being supplied during the supply of silicon material and oxygen material by means of an organic silicon precursor material. The layer of oxygen material and nitrogen material is formed in such a manner that an area free of material remains between the electrically conductive structures. An intermediate layer including an electrically insulating material is formed over the layer of oxygen material and nitrogen material. A covering layer is selectively formed over the intermediate layer such that the area free of material between the electrically conductive structures is sealed from the environment and forms a cavity.Type: GrantFiled: January 22, 2005Date of Patent: July 13, 2010Assignee: Infineon Technologies AGInventors: Zvonimir Gabric, Werner Pamler, Guenther Schindler
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Publication number: 20080308898Abstract: A method for producing a layer arrangement is disclosed. A layer of oxygen material and nitrogen material is formed over a substrate that has a plurality of electrically conductive structures and/or over a part of a surface of the electrically conductive structures. The layer is formed using a plasma-enhanced chemical vapor deposition process with nitrogen material being supplied during the supply of silicon material and oxygen material by means of an organic silicon precursor material. The layer of oxygen material and nitrogen material is formed in such a manner that an area free of material remains between the electrically conductive structures. An intermediate layer including an electrically insulating material is formed over the layer of oxygen material and nitrogen material. A covering layer is selectively formed over the intermediate layer such that the area free of material between the electrically conductive structures is sealed from the environment and forms a cavity.Type: ApplicationFiled: January 22, 2005Publication date: December 18, 2008Inventors: Zvonimir Gabric, Werner Pamler, Guenther Schindler
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Patent number: 7422940Abstract: A process for producing a layer arrangement, in which a plurality of electrically conductive structures are formed on a substrate, a first electrically insulating layer is formed on the plurality of electrically conductive structures, in such a manner than trenches are formed between mutually adjacent regions of the first electrically insulating layer, electrically insulating structures are formed in the trenches between the adjacent regions of the first electrically insulating layer, material of the first electrically insulating layer is removed, so that airgaps are formed between the electrically insulating structures and the electrically conductive structures, and a second electrically insulating layer is formed on the electrically conductive structures and on the electrically insulating structures, in such a manner that the second electrically insulating layer spans adjacent electrically conductive structures and electrically insulating structures.Type: GrantFiled: August 1, 2005Date of Patent: September 9, 2008Assignee: Infineon Technologies AGInventors: Gunther Schindler, Werner Pamler
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Publication number: 20070246831Abstract: In a method for manufacturing a layer arrangement, a plurality of electrically conductive structures are embedded in a substrate. Material of the substrate is removed at least between adjacent electrically conductive structures. An interlayer is formed on at least one portion of sidewalls of each of the electrically conductive structures. A first layer is formed on the interlayer where an upper partial region of the interlayer remaining free of a covering with the first layer. An electrically insulating second layer is formed selectively on that partial region of the interlayer which is free of the first layer, in such a way that the electrically insulating second layer bridges adjacent electrically conductive structures such that air gaps are formed between adjacent electrically conductive structures.Type: ApplicationFiled: April 12, 2007Publication date: October 25, 2007Inventors: Zvonimir Gabric, Werner Pamler, Guenther Schindler, Gernot Steinlesberger, Andreas Stich, Martin Traving, Eugen Unger
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Patent number: 7259441Abstract: A pattern of voids in an integrated circuit having a first layer, a first layer surface and adjacent lands on the first layer surface, the adjacent lands enclosing spaces and including a second layer of a first isolation material and a third layer of a second isolation material arranged on the second layer. The pattern of voids has a fourth layer of a third isolation material which closes off at least some of the spaces and cannot be deposited on the first isolation material. The fourth layer is arranged on the third layer and has a second layer surface. Spaces that are not closed off by means of the fourth layer are filled with electrically conductive material. In the method for producing a pattern of voids in an integrated circuit, a second layer of a first isolation material is applied to a first layer surface of a first layer. A third layer of a second isolation material is applied to the second layer, the third layer acquiring a second layer surface which is arranged parallel to the first layer surface.Type: GrantFiled: February 15, 2002Date of Patent: August 21, 2007Assignee: Infineon Technologies AGInventors: Werner Pamler, Siegfried Schwarzl, Zvonimir Gabric
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Publication number: 20070120263Abstract: A conductor track arrangement includes a substrate, at least two conductor tracks, a cavity and a resist layer that covers the conductor tracks and closes off the cavity. By forming carrier tracks with a width less than a width of the conductor tracks, air gaps can also be formed laterally underneath the conductor tracks for reducing the coupling capacitances and the signal delays in a self-aligning manner.Type: ApplicationFiled: August 18, 2006Publication date: May 31, 2007Inventors: Zvonimir Gabric, Werner Pamler, Guenther Schindler, Andreas Stich
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Publication number: 20060199368Abstract: An interconnect arrangement and fabrication method are described. The interconnect arrangement includes an electrically conductive mount substrate, a dielectric layer formed on the mount substrate, and an electrically conductive interconnect formed on the dielectric layer. At least a portion of the dielectric layer under the interconnect contains a cavity. To fabricate the interconnect arrangement, a sacrificial layer is formed on the mount substrate and the interconnect layer is formed on the sacrificial layer. The interconnect layer and the sacrificial layer are structured to produce a structured interconnect on the structured sacrificial layer. A porous dielectric layer is formed on a surface of the mount substrate and of the structured interconnect as well as the sacrificial layer. The sacrificial layer is then removed to form the cavity under the interconnect.Type: ApplicationFiled: February 22, 2006Publication date: September 7, 2006Inventors: Manfred Engelhardt, Werner Pamler, Guenther Schindler
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Patent number: 7045070Abstract: The electrode configuration includes at least one structured layer. A mask is produced on the layer to be structured and the layer is dry etched. The mask is at least slightly etchable by dry etching. The mask contains a metal silicide, a metal nitride or a metal oxide.Type: GrantFiled: August 24, 2000Date of Patent: May 16, 2006Assignee: Infineon Technologies AGInventors: Volker Weinrich, Manfred Engelhardt, Werner Pamler, Hermann Wendt
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Patent number: 7033926Abstract: An interconnect arrangement comprises a substrate made from a first insulating material with a substrate surface, at least two interconnects which are arranged next to one another in the substrate, a buffer layer made from a second insulating material above the substrate and comprising a buffer-layer surface, which is parallel to the substrate surface, at least one cavity, which is arranged between the interconnects and, with respect to the buffer-layer surface, extends deeper into the substrate than the interconnects, and a covering layer made from a third insulating material, which is arranged above the buffer layer and completely closes off the cavity with respect to the buffer-layer surface.Type: GrantFiled: August 9, 2002Date of Patent: April 25, 2006Assignee: Infineon Technologies, AGInventors: Günther Schindler, Werner Pamler, Zvonimir Gabric
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Patent number: 7023063Abstract: A method referred to as a “cellular damascene method” utilizes a multiplicity of regularly arranged closed cavities referred to as “cells”, which are produced in a patterning layer. The dimensions of the cavities are on the order of magnitude of the microstructures to be produced. Selected cavities are opened by providing a mask and partitions situated between adjacent opened cavities are removed to provide trenches and holes which are filled with the material of the microstructure to be fabricated. Protruding material is removed by means of a chemical-mechanical polishing step. The microstructures are, in particular, interconnects and contact holes of integrated circuit.Type: GrantFiled: October 25, 2004Date of Patent: April 4, 2006Assignee: Infineon Technologies AGInventors: Zvonimir Gabric, Werner Pamler, Siegfried Schwarzl
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Publication number: 20060022345Abstract: A process for producing a layer arrangement, in which a plurality of electrically conductive structures are formed on a substrate, a first electrically insulating layer is formed on the plurality of electrically conductive structures, in such a manner than trenches are formed between mutually adjacent regions of the first electrically insulating layer, electrically insulating structures are formed in the trenches between the adjacent regions of the first electrically insulating layer, material of the first electrically insulating layer is removed, so that airgaps are formed between the electrically insulating structures and the electrically conductive structures, and a second electrically insulating layer is formed on the electrically conductive structures and on the electrically insulating structures, in such a manner that the second electrically insulating layer spans adjacent electrically conductive structures and electrically insulating structures.Type: ApplicationFiled: August 1, 2005Publication date: February 2, 2006Applicant: Infineon Technologies AGInventors: Gunther Schindler, Werner Pamler
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Publication number: 20050054184Abstract: A method referred to as a “cellular damascene method” utilizes a multiplicity of regularly arranged closed cavities referred to as “cells”, which are produced in a patterning layer. The dimensions of the cavities are on the order of magnitude of the microstructures to be produced. Selected cavities are opened by providing a mask and partitions situated between adjacent opened cavities are removed to provide trenches and holes which are filled with the material of the microstructure to be fabricated. Protruding material is removed by means of a chemical-mechanical polishing step. The microstructures are, in particular, interconnects and contact holes of integrated circuit.Type: ApplicationFiled: October 25, 2004Publication date: March 10, 2005Inventors: Zvonimir Gabric, Werner Pamler, Siegfried Schwarzl
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Patent number: 6825098Abstract: A method referred to as a “cellular damascene method” utilizes a multiplicity of regularly arranged closed cavities referred to as “cells”, which are produced in a patterning layer. The dimensions of the cavities are on the order of magnitude of the microstructures to be produced. Selected cavities are opened by providing a mask and partitions situated between adjacent opened cavities are removed to provide trenches and holes which are filled with the material of the microstructure to be fabricated. Protruding material is removed by means of a chemical-mechanical polishing step. The microstructures are, in particular, interconnects and contact holes of integrated circuit.Type: GrantFiled: June 25, 2003Date of Patent: November 30, 2004Assignee: Infineon Technologies AGInventors: Zvonimir Gabric, Werner Pamler, Siegfried Schwarzl
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Patent number: 6737692Abstract: A method for improving the adhesion between a noble metal layer and an insulation layer includes configuring a silicon layer between the noble metal layer and the insulation layer. The silicon layer is siliconized and oxidized by a thermal treatment in an oxidative environment, resulting in an oxidized silicide layer with high intermixing of the noble metal and the formed oxide. The relatively large inner surface achieved as a result improves the adhesion between the noble metal layer and the insulation layer.Type: GrantFiled: February 20, 2003Date of Patent: May 18, 2004Assignee: Infineon Technologies AGInventors: Zvonimir Gabric, Werner Pamler, Volker Weinrich
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Publication number: 20040084749Abstract: A pattern of voids in an integrated circuit having a first layer, a first layer surface and adjacent lands on the first layer surface, the adjacent lands enclosing spaces and including a second layer of a first isolation material and a third layer of a second isolation material arranged on the second layer. The pattern of voids has a fourth layer of a third isolation material which closes off at least some of the spaces and cannot be deposited on the first isolation material. The fourth layer is arranged on the third layer and has a second layer surface. Spaces that are not closed off by means of the fourth layer are filled with electrically conductive material. In the method for producing a pattern of voids in an integrated circuit, a second layer of a first isolation material is applied to a first layer surface of a first layer. A third layer of a second isolation material is applied to the second layer, the third layer acquiring a second layer surface which is arranged parallel to the first layer surface.Type: ApplicationFiled: November 17, 2003Publication date: May 6, 2004Inventors: Werner Pamler, Siegfried Schwarzl, Zvonimir Gabric
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Publication number: 20040033652Abstract: A method referred to as a “cellular damascene method” utilizes a multiplicity of regularly arranged closed cavities referred to as “cells”, which are produced in a patterning layer. The dimensions of the cavities are on the order of magnitude of the microstructures to be produced. Selected cavities are opened by providing a mask and partitions situated between adjacent opened cavities are removed to provide trenches and holes which are filled with the material of the microstructure to be fabricated. Protruding material is removed by means of a chemical-mechanical polishing step. The microstructures are, in particular, interconnects and contact holes of integrated circuit.Type: ApplicationFiled: June 25, 2003Publication date: February 19, 2004Inventors: Zvonimir Gabric, Werner Pamler, Siegfried Schwarzl
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Patent number: 6686643Abstract: Metal structures that can be produced by a damascene process are disposed in a first insulating layer and a second insulating layer is disposed above the latter. There is in each case at least one cavity which is disposed between the metal structures, is disposed in the first insulating layer and is covered by the second insulating layer. The cavities and the metal structures are produced next to one another by self-aligned process steps.Type: GrantFiled: November 29, 2000Date of Patent: February 3, 2004Assignee: Infineon Technologies AGInventors: Siegfried Schwarzl, Werner Pamler, Zvonimir Gabric