Patents by Inventor Wesley Natzle
Wesley Natzle has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7705385Abstract: A method of selectively forming a germanium structure within semiconductor manufacturing processes removes the native oxide from a nitride surface in a chemical oxide removal (COR) process and then exposes the heated nitride and oxide surface to a heated germanium containing gas to selectively form germanium only on the nitride surface but not the oxide surface.Type: GrantFiled: September 12, 2005Date of Patent: April 27, 2010Assignee: International Business Machines CorporationInventors: Ashima Chakravarti, Anthony Chou, Toshiharu Furukawa, Steven Holmes, Wesley Natzle
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Patent number: 7567700Abstract: A method of processing a wafer is presented that includes creating a pre-processing measurement map using measured metrology data for the wafer including metrology data for at least one isolated structure on the wafer, metrology data for at least one nested structure on the wafer, or mask data. At least one pre-processing prediction map is calculated for the wafer. A pre-processing confidence map is calculated for the wafer. The pre-processing confidence map includes a set of confidence data for the plurality of dies on the wafer. A prioritized measurement site is determined when the confidence data for one or more dies is not within the confidence limits. A new measurement recipe that includes the prioritized measurement site is then created.Type: GrantFiled: March 28, 2006Date of Patent: July 28, 2009Assignees: Tokyo Electron Limited, International Business Machines CorporationInventors: Merritt Funk, Radha Sundararajan, Daniel Joseph Prager, Wesley Natzle
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Patent number: 7502709Abstract: A method of monitoring a dual damascene procedure that includes calculating a pre-processing confidence map for a damascene process, the pre-processing confidence map including confidence data for a first set of dies on the wafer. An expanded pre-processing measurement recipe is established for the damascene process when one or more values in the pre-processing confidence map are not within confidence limits established for the damascene process. A reduced pre-processing measurement recipe for the first damascene process is established when one or more values in the pre-processing confidence map are within confidence limits established for the damascene process.Type: GrantFiled: March 28, 2006Date of Patent: March 10, 2009Assignees: Tokyo Electron, Ltd., International Business Machines CorporationInventors: Merritt Funk, Radha Sundararajan, Daniel Joseph Prager, Wesley Natzle
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Patent number: 7470629Abstract: There is provided a method for fabricating a FinFET in which a self-limiting reaction is employed to produce a unique and useful structure that may be detectable with simple failure analysis techniques. The structure is an improved vertical fin with a gently sloping base portion that is sufficient to reduce or prevent the formation of an undercut area in the base of the vertical fin. The structure is formed via the self-limiting properties of the reaction so that the products of the reaction form both vertically on a surface of the vertical fin and horizontally on a surface of an insulating layer (e.g., buried oxide). The products preferentially accumulate faster at the base of the vertical fin where the products from both the horizontal and vertical surfaces overlap. This accumulation or build-up results from a volume expansion stemming from the reaction.Type: GrantFiled: October 26, 2005Date of Patent: December 30, 2008Assignee: International Business Machines CorporationInventors: Wesley Natzle, Bruce B. Doris
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Patent number: 7451011Abstract: The invention relates to controlling a semiconductor processing system. Among other things, the invention relates to a run-to-run controller to create virtual modules to control a multi-pass process performed by a multi-chamber tool during the processing of a semiconductor wafer.Type: GrantFiled: August 27, 2004Date of Patent: November 11, 2008Inventors: Merritt Funk, Wesley Natzle
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Publication number: 20080093629Abstract: Disclosed are embodiments of a MOSFET with defined halos that are bound to defined source/drain extensions and a method of forming the MOSFET. A semiconductor layer is etched to form recesses that undercut a gate dielectric layer. A low energy implant forms halos. Then, a COR pre-clean is performed and the recesses are filled by epitaxial deposition. The epi can be in-situ doped or subsequently implanted to form source/drain extensions. Alternatively, the etch is immediately followed by the COR pre-clean, which is followed by epitaxial deposition to fill the recesses. During the epitaxial deposition process, the deposited material is doped to form in-situ doped halos and, then, the dopant is switched to form in-situ doped source/drain extensions adjacent to the halos. Alternatively, after the in-situ doped halos are formed the deposition process is performed without dopants and an implant is used to form source/drain extensions.Type: ApplicationFiled: December 13, 2007Publication date: April 24, 2008Applicant: International Business Machines CorporationInventors: Huajie Chen, Judson Holt, Rangarajan Jagannathan, Wesley Natzle, Michael Sievers, Richard Wise
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Patent number: 7344965Abstract: A method for making dual pre-doped gate stacks used in semiconductor applications such as complementary metal oxide semiconductor (CMOS) devices and metal oxide semiconductor field effect transistors (MOSFETs) is provided. The method involves providing at least one pre-doped conductive layer, such as poly silicon (poly-Si), on a gate stack and etching by exposing the conductive layer to an etching composition comprising at least one carbon containing gas. The carbon containing gas can be selected from gases having the general formula CxHy, such as, for example, CH4, C2H2, C2H4, and C2H6. The carbon containing gas can further be selected from gases having the general formula CxHyA, wherein A can represent one or more additional substituents selected from O, N, P, S, F, Cl, Br, and I. The processes can result in dual pre-doped gate stacks having essentially vertical sidewalls and further having a width of at least about 3 nm, such as from about 5 nm to about 150 nm.Type: GrantFiled: December 10, 2003Date of Patent: March 18, 2008Assignee: International Business Machines CorporationInventors: Ying Zhang, Timothy Joseph Dalton, Wesley Natzle
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Publication number: 20080027577Abstract: A system, method and program product for correcting a deviation of a dimension of a feature from a target in a semiconductor process, are disclosed. The invention determines an origin of a deviation in a feature dimension from a target dimension regardless of whether it is based on processing or metrology. Adjustments for wafer processing variation of previous process tools can be fed forward, and adjustments for the process and/or integrated metrology tools may be fed back automatically during the processing of semiconductor wafers. The invention implements process reference wafers to determine the origin in one mode, and measurement reference wafers to determine the origin of deviations in another mode.Type: ApplicationFiled: October 2, 2007Publication date: January 31, 2008Inventors: David Horak, Wesley Natzle, Merritt Funk, Kevin Lally, Daniel Prager
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Patent number: 7292906Abstract: A processing method of processing a substrate is presented that includes: receiving pre-process data, wherein the pre-process data comprises a desired process result and actual measured data for the substrate; determining a required process result, wherein the required process result comprises the difference between the desired process result and the actual measured data; creating a new process recipe by modifying a nominal recipe obtained from a processing tool using at least one of a static recipe and a formula model, wherein the new process recipe provides a new process result that is approximately equal to the required process result; and sending the new process recipe to the processing tool and the substrate.Type: GrantFiled: July 14, 2004Date of Patent: November 6, 2007Assignee: Tokyo Electron LimitedInventors: Merritt Funk, Kevin Augustine Pinto, Asao Yamashita, Wesley Natzle
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Publication number: 20070237383Abstract: A method of processing a wafer is presented that includes creating a pre-processing measurement map using measured metrology data for the wafer including metrology data for at least one isolated structure on the wafer, metrology data for at least one nested structure on the wafer, or mask data. At least one pre-processing prediction map is calculated for the wafer. A pre-processing confidence map is calculated for the wafer. The pre-processing confidence map includes a set of confidence data for the plurality of dies on the wafer. A prioritized measurement site is determined when the confidence data for one or more dies is not within the confidence limits. A new measurement recipe that includes the prioritized measurement site is then created.Type: ApplicationFiled: March 28, 2006Publication date: October 11, 2007Inventors: Merritt Funk, Radha Sundararajan, Daniel Prager, Wesley Natzle
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Publication number: 20070238201Abstract: A method of processing a wafer is presented that includes creating a pre-processing measurement map using measured metrology data for the wafer including metrology data for at least one isolated structure on the wafer, metrology data for at least one nested structure on the wafer, bi-layer mask data, and BARC layer data. At least one pre-processing prediction map is calculated for the wafer. A pre-processing confidence map is calculated for the wafer. The pre-processing confidence map includes a set of confidence data for the plurality of dies on the wafer. A prioritized measurement site is determined when the confidence data for one or more dies is not within the confidence limits. A new measurement recipe that includes the prioritized measurement site is then created.Type: ApplicationFiled: March 28, 2006Publication date: October 11, 2007Inventors: Merritt Funk, Radha Sundararajan, Daniel Prager, Wesley Natzle
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Publication number: 20070231930Abstract: A method of monitoring a dual damascene procedure that includes calculating a pre-processing confidence map for a damascene process, the pre-processing confidence map including confidence data for a first set of dies on the wafer. An expanded pre-processing measurement recipe is established for the damascene process when one or more values in the pre-processing confidence map are not within confidence limits established for the damascene process. A reduced pre-processing measurement recipe for the first damascene process is established when one or more values in the pre-processing confidence map are within confidence limits established for the damascene process.Type: ApplicationFiled: March 28, 2006Publication date: October 4, 2007Inventors: Merritt Funk, Radha Sundararajan, Daniel Prager, Wesley Natzle
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Patent number: 7212878Abstract: The invention relates to controlling a semiconductor processing system. Among other things, the invention relates to a run-to-run controller to create virtual modules to control a multi-pass process performed by a multi-chamber tool during the processing of a semiconductor wafer.Type: GrantFiled: August 27, 2004Date of Patent: May 1, 2007Assignees: Tokyo Electron Limited, International Business Machines CorporationInventors: Merritt Funk, Wesley Natzle
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Publication number: 20070059894Abstract: A method of selectively forming a germanium structure within semiconductor manufacturing processes removes the native oxide from a nitride surface in a chemical oxide removal (COR) process and then exposes the heated nitride and oxide surface to a heated germanium containing gas to selectively form germanium only on the nitride surface but not the oxide surface.Type: ApplicationFiled: September 12, 2005Publication date: March 15, 2007Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ashima Chakravarti, Anthony Chou, Toshiharu Furukawa, Steven Holmes, Wesley Natzle
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Patent number: 7176534Abstract: The present invention provides a method for fabricating low-resistance, sub-0.1 ?m channel T-gate MOSFETs that do not exhibit any poly depletion problems. The inventive method employs a damascene-gate processing step and a chemical oxide removal etch to fabricate such MOSFETs. The chemical oxide removal may be performed in a vapor containing HF and NH3 or a plasma containing HF and NH3.Type: GrantFiled: September 11, 2003Date of Patent: February 13, 2007Assignee: International Business Machines CorporationInventors: Hussein I. Hanafi, Wesley Natzle
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Publication number: 20060211244Abstract: A cluster tool is provided for the implementing of a clustered and integrated surface pre-cleaning of the surface of semiconductor devices. More particularly, there is provided a cluster tool and a method of utilization thereof in an integrated semiconductor device surface pre-cleaning, which is directed towards a manufacturing aspect in which a chamber for performing a dry processing chemical oxide removal (COR) on the semiconductor device surface is clustered with other tools, such as a metal deposition tool for silicide or contact formation, including the provision of a vacuum transfer module in the cluster tool.Type: ApplicationFiled: March 18, 2005Publication date: September 21, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Sadanand Deshpande, Ying Li, Kevin Mello, Renee Mo, Wesley Natzle, Kirk Peterson, Robert Purtell
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Publication number: 20060183308Abstract: A method for making dual pre-doped gate stacks used in semiconductor applications such as complementary metal oxide semiconductor (CMOS) devices and metal oxide semiconductor field effect transistors (MOSFETs) is provided. The method involves providing at least one pre-doped conductive layer, such as poly silicon (poly-Si), on a gate stack and etching by exposing the conductive layer to an etching composition comprising at least one carbon containing gas. The carbon containing gas can be selected from gases having the general formula CxHy, such as, for example, CH4, C2H2, C2H4, and C2H6. The carbon containing gas can further be selected from gases having the general formula CxHyA, wherein a can represent one or more additional substituents selected from O, N, P, S, F, Cl, Br, and I. The processes can result in dual pre-doped gate stacks having essentially vertical sidewalls and further having a width of at least about 3 nm, such as from about 5 nm to about 150 nm.Type: ApplicationFiled: December 10, 2003Publication date: August 17, 2006Inventors: Ying Zhang, Timothy Dalton, Wesley Natzle
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Publication number: 20060166416Abstract: A chemical composition and method for providing uniform and consistent etching of gate stacks on a semiconductor wafer, whereby the composition includes an etchant and an added ballast gas added. The gate stacks are formed using this combined etchant and ballast gas composition. The ballast gas may either be similar to, or the equivalent of, a gaseous byproduct generated within the processing chamber. The ballast gas is added in either an overload amount, or in an amount sufficient to compensate for varying pattern factor changes across the water. This etchant and added ballast gas form a substantially homogeneous etchant across the entire wafer, thereby accommodating for or compensating for these pattern factor differences. When etching the wafer using this homogeneous etchant, a passivation layer is formed on exposed wafer surfaces. The passivation layer protects the lateral sidewalls of the gate stacks during etch to result in straighter gate stacks.Type: ApplicationFiled: January 27, 2005Publication date: July 27, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Timothy Dalton, Wesley Natzle, Paul Pastel, Richard Wise, Hongwen Yan, Ying Zhang
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Patent number: 7049662Abstract: There is provided a method for fabricating a FinFET in which a self-limiting reaction is employed to produce a unique and useful structure that may be detectable with simple failure analysis techniques. The structure is an improved vertical fin with a gently sloping base portion that is sufficient to reduce or prevent the formation of an undercut area in the base of the vertical fin. The structure is formed via the self-limiting properties of the reaction so that the products of the reaction form both vertically on a surface of the vertical fin and horizontally on a surface of an insulating layer (e.g., buried oxide). The products preferentially accumulate faster at the base of the vertical fin where the products from both the horizontal and vertical surfaces overlap. This accumulation or build-up results from a volume expansion stemming from the reaction.Type: GrantFiled: November 26, 2003Date of Patent: May 23, 2006Assignee: International Business Machines CorporationInventors: Wesley Natzle, Bruce B. Doris
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Publication number: 20060096951Abstract: An apparatus is provided which includes a holder operable to retain an article for interaction with a medium. The article has a first portion and a second portion, and the medium is such that the interaction alters the article in a temperature-dependent manner. First and second temperature-modifying elements are maintained by the holder adjacent to the first and second portions of the article to facilitate heat transfer between each temperature-modifying element and the adjacent portion of the article. The apparatus also includes a controller which is operable to maintain the first and second temperature-modifying elements at first and second independently controlled temperatures, respectively, such that the rate of interaction of the medium with each portion of the article is variable in a manner dependent upon the temperature of the adjacent temperature-modifying element.Type: ApplicationFiled: October 29, 2004Publication date: May 11, 2006Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, TOKYO ELECTRON LIMITEDInventors: Wesley Natzle, William Chu, David Horak, Arthur LaFlamme, Tomoyasu Masayuki, Akihisa Sekiguchi