Patents by Inventor Wilhelm Haller
Wilhelm Haller has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10528323Abstract: A circuit is provided for addition of multiple binary numbers. The circuit includes a 4-to-2-compressor configured for calculating a compressed representation from four binary numbers received via operand inputs of the 4-to-2-compressor. The 4-to-2-compressor includes a first sub-circuit and a second sub-circuit. Each of the first sub-circuit and the second sub-circuit is configured for transmitting a bitwise inverted representation, of a compressed representation, from three binary numbers.Type: GrantFiled: September 28, 2018Date of Patent: January 7, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Manuel Beck, Wilhelm Haller, Ulrich Krauch, Kurt Lind, Friedrich Schroeder
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Patent number: 10317465Abstract: An integrated circuit chip includes at least two integrated circuits, at least three scan chains, and a multiplexor circuitry. Each integrated circuit includes an integrated circuit input port and an integrated circuit output port. The scan chains and the integrated circuits are coupled by default with a series chain having integrated circuits and scan chains alternating each other. The series chain starts with an initial scan chain and ends with the end scan chain. Each scan chain except the initial one includes a first scan chain input port coupled by default with the integrated circuit output port of the respective adjacent integrated circuit. Each scan chain except the end one includes a first scan chain output port coupled by default with the integrated circuit input port of the respective adjacent integrated circuit.Type: GrantFiled: April 12, 2018Date of Patent: June 11, 2019Assignee: International Business Machines CorporationInventors: Wilhelm Haller, Markus Kaltenbach, Ulrich Krauch, Nicolas Maeding, Christian Zoellin
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Publication number: 20190034165Abstract: A circuit is provided for addition of multiple binary numbers. The circuit includes a 4-to-2-compressor configured for calculating a compressed representation from four binary numbers received via operand inputs of the 4-to-2-compressor. The 4-to-2-compressor includes a first sub-circuit and a second sub-circuit. Each of the first sub-circuit and the second sub-circuit is configured for transmitting a bitwise inverted representation, of a compressed representation, from three binary numbers.Type: ApplicationFiled: September 28, 2018Publication date: January 31, 2019Inventors: Manuel BECK, Wilhelm HALLER, Ulrich KRAUCH, Kurt LIND, Friedrich SCHROEDER
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Patent number: 10168991Abstract: A circuit is provided for addition of multiple binary numbers. The circuit includes a 4-to-2-compressor configured for calculating a compressed representation from four binary numbers received via operand inputs of the 4-to-2-compressor. The 4-to-2-compressor includes a first sub-circuit and a second sub-circuit. Each of the first sub-circuit and the second sub-circuit is configured for transmitting a bitwise inverted representation, of a compressed representation, from three binary numbers.Type: GrantFiled: December 16, 2016Date of Patent: January 1, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Manuel Beck, Wilhelm Haller, Ulrich Krauch, Kurt Lind, Friedrich Schroeder
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Publication number: 20180231607Abstract: An integrated circuit chip includes at least two integrated circuits, at least three scan chains, and a multiplexor circuitry. Each integrated circuit includes an integrated circuit input port and an integrated circuit output port. The scan chains and the integrated circuits are coupled by default with a series chain having integrated circuits and scan chains alternating each other. The series chain starts with an initial scan chain and ends with the end scan chain. Each scan chain except the initial one includes a first scan chain input port coupled by default with the integrated circuit output port of the respective adjacent integrated circuit. Each scan chain except the end one includes a first scan chain output port coupled by default with the integrated circuit input port of the respective adjacent integrated circuit.Type: ApplicationFiled: April 12, 2018Publication date: August 16, 2018Inventors: Wilhelm Haller, Markus Kaltenbach, Ulrich Krauch, Nicolas Maeding, Christian Zoellin
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Patent number: 10031995Abstract: An end point report for a design of an electronic circuit may be analyzed. Results of a static timing analysis run are loaded, a path from the loaded results is selected, and technology specific context data is provided. Additionally, a determination is made for every test point of the selected path of design quality parameters for determining a design problem area, and a determination is made for every design problem area, of a root cause by analyzing design problem area data in comparison to related ones of the technology specific context data.Type: GrantFiled: September 18, 2015Date of Patent: July 24, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Wilhelm Haller, Kurt Lind, Friedrich Schroeder, Stefan Zimmermann
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Patent number: 10006965Abstract: An integrated circuit chip includes at least two integrated circuits, at least three scan chains, and a multiplexor circuitry. Each integrated circuit includes an integrated circuit input port and an integrated circuit output port. The scan chains and the integrated circuits are coupled by default with a series chain having integrated circuits and scan chains alternating each other. The series chain starts with an initial scan chain and ends with the end scan chain. Each scan chain except the initial one includes a first scan chain input port coupled by default with the integrated circuit output port of the respective adjacent integrated circuit. Each scan chain except the end one includes a first scan chain output port coupled by default with the integrated circuit input port of the respective adjacent integrated circuit.Type: GrantFiled: September 16, 2016Date of Patent: June 26, 2018Assignee: International Business Machines CorporationInventors: Wilhelm Haller, Markus Kaltenbach, Ulrich Krauch, Nicolas Maeding, Christian Zoellin
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Publication number: 20180088907Abstract: A circuit is provided for addition of multiple binary numbers. The circuit includes a 4-to-2-compressor configured for calculating a compressed representation from four binary numbers received via operand inputs of the 4-to-2-compressor. The 4-to-2-compressor includes a first sub-circuit and a second sub-circuit. Each of the first sub-circuit and the second sub-circuit is configured for transmitting a bitwise inverted representation, of a compressed representation, from three binary numbers.Type: ApplicationFiled: December 16, 2016Publication date: March 29, 2018Inventors: Manuel BECK, Wilhelm HALLER, Ulrich KRAUCH, Kurt LIND, Friedrich SCHROEDER
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Publication number: 20170083658Abstract: An end point report for a design of an electronic circuit may be analyzed. Results of a static timing analysis run are loaded, a path from the loaded results is selected, and technology specific context data is provided. Additionally, a determination is made for every test point of the selected path of design quality parameters for determining a design problem area, and a determination is made for every design problem area, of a root cause by analyzing design problem area data in comparison to related ones of the technology specific context data.Type: ApplicationFiled: September 18, 2015Publication date: March 23, 2017Inventors: Wilhelm Haller, Kurt Lind, Friedrich Schroeder, Stefan Zimmermann
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Publication number: 20170003345Abstract: An integrated circuit chip includes at least two integrated circuits, at least three scan chains, and a multiplexor circuitry. Each integrated circuit includes an integrated circuit input port and an integrated circuit output port. The scan chains and the integrated circuits are coupled by default with a series chain having integrated circuits and scan chains alternating each other. The series chain starts with an initial scan chain and ends with the end scan chain. Each scan chain except the initial one includes a first scan chain input port coupled by default with the integrated circuit output port of the respective adjacent integrated circuit. Each scan chain except the end one includes a first scan chain output port coupled by default with the integrated circuit input port of the respective adjacent integrated circuit.Type: ApplicationFiled: September 16, 2016Publication date: January 5, 2017Inventors: Wilhelm Haller, Markus Kaltenbach, Ulrich Krauch, Nicolas Maeding, Christian Zoellin
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Patent number: 9506986Abstract: An integrated circuit chip includes at least two integrated circuits, at least three scan chains, and a multiplexor circuitry. Each integrated circuit includes an integrated circuit input port and an integrated circuit output port. The scan chains and the integrated circuits are coupled by default with a series chain having integrated circuits and scan chains alternating each other. The series chain starts with an initial scan chain and ends with the end scan chain. Each scan chain except the initial one includes a first scan chain input port coupled by default with the integrated circuit output port of the respective adjacent integrated circuit. Each scan chain except the end one includes a first scan chain output port coupled by default with the integrated circuit input port of the respective adjacent integrated circuit.Type: GrantFiled: September 4, 2014Date of Patent: November 29, 2016Assignee: International Business Machines CorporationInventors: Wilhelm Haller, Markus Kaltenbach, Ulrich Krauch, Nicolas Maeding, Christian Zoellin
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Patent number: 9058456Abstract: An improved method for fixing an early mode slack in a hierarchically designed hardware device with at least one source macro, an integration unit and at least one sink macro comprises: Loading hardware design timing data to determine pins where an early mode slack fix can be applied to fix an early mode slack; for each such pin determining a location across the design hierarchy for the early mode slack fix by calculating a weight value for each of a selection of fix locations of the early mode slack based on absolute values of arrival times of data signals, ratio and difference between arrival times of late mode data signals and early mode data signals; and assigning the early mode slack fix to the determined location based on said weight value.Type: GrantFiled: September 24, 2013Date of Patent: June 16, 2015Assignee: International Business Machines CorporationInventors: Wilhelm Haller, Ulrich Krauch, Kurt Lind, Alexander Woerner
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Publication number: 20150160293Abstract: An integrated circuit chip includes at least two integrated circuits, at least three scan chains, and a multiplexor circuitry. Each integrated circuit includes an integrated circuit input port and an integrated circuit output port. The scan chains and the integrated circuits are coupled by default with a series chain having integrated circuits and scan chains alternating each other. The series chain starts with an initial scan chain and ends with the end scan chain. Each scan chain except the initial one includes a first scan chain input port coupled by default with the integrated circuit output port of the respective adjacent integrated circuit. Each scan chain except the end one includes a first scan chain output port coupled by default with the integrated circuit input port of the respective adjacent integrated circuit.Type: ApplicationFiled: September 4, 2014Publication date: June 11, 2015Inventors: Wilhelm Haller, Markus Kaltenbach, Ulrich Krauch, Nicolas Maeding, Christian Zoellin
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Patent number: 8701059Abstract: The invention relates to a method and a system for repartitioning a formalized hardware description of a hierarchically structured electronic circuit design unit comprising a plurality of macros in terms of latch macros and combinatorial macros. In a first step, each macro is dissected into latch macros and signal cones in such a way that each signal cone comprises signals linking macro input/output to a latch output/input, and each latch macro comprises at least one latch, each primary input an output of said latch macro coinciding with an input or an output of a latch within said latch macro. Subsequently, combinatorial macros are created by merging combinatorial signal cones along unit signal paths.Type: GrantFiled: March 1, 2013Date of Patent: April 15, 2014Assignee: International Business Machines CorporationInventors: Elmar Gaugler, Wilhelm Haller, Friedhelm Kessler
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Publication number: 20140089880Abstract: An improved method for fixing an early mode slack in a hierarchically designed hardware device with at least one source macro, an integration unit and at least one sink macro comprises: Loading hardware design timing data to determine pins where an early mode slack fix can be applied to fix an early mode slack; for each such pin determining a location across the design hierarchy for the early mode slack fix by calculating a weight value for each of a selection of fix locations of the early mode slack based on absolute values of arrival times of data signals, ratio and difference between arrival times of late mode data signals and early mode data signals; and assigning the early mode slack fix to the determined location based on said weight value.Type: ApplicationFiled: September 24, 2013Publication date: March 27, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Wilhelm Haller, Ulrich Krauch, Kurt Lind, Alexander Woerner
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Patent number: 8612500Abstract: A method to generate a magnitude result of a mathematic operation of two decimal operands within one cycle in a decimal arithmetic logic unit structure, wherein the decimal operands are in hexadecimal sign magnitude format.Type: GrantFiled: January 14, 2008Date of Patent: December 17, 2013Assignee: International Business Machines CorporationInventors: Wilhelm Haller, Ulrich Krauch, Guenter Mayer, Eric M. Schwarz
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Publication number: 20130239075Abstract: The invention relates to a method and a system for repartitioning a formalized hardware description of a hierarchically structured electronic circuit design unit comprising a plurality of macros in terms of latch macros and combinatorial macros. In a first step, each macro is dissected into latch macros and signal cones in such a way that each signal cone comprises signals linking macro input/output to a latch output/input, and each latch macro comprises at least one latch, each primary input an output of said latch macro coinciding with an input or an output of a latch within said latch macro. Subsequently, combinatorial macros are created by merging combinatorial signal cones along unit signal paths.Type: ApplicationFiled: March 1, 2013Publication date: September 12, 2013Applicant: International Business Machines CorporationInventors: Elmar Gaugler, Wilhelm Haller, Friedhelm Kessler
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Publication number: 20130227250Abstract: Some example embodiments include an apparatus for comparing a first operand to a second operand. The apparatus includes a SIMD accelerator configured to compare first multiple parts (e.g., bytes) of first operand to second multiple parts (e.g., bytes) of the second operand. The SIMD accelerator includes a ones' complement subtraction logic and a twos' complement logic configured to perform logic operations on the multiple parts of the first operand and the multiple parts of the second operand to generate a group of carry out and propagate data across bits of the multiple parts. At least a portion of the group of carry out and propagate data is reused in the group of logic operations.Type: ApplicationFiled: February 24, 2012Publication date: August 29, 2013Applicant: International Business Machines CorporationInventors: Wilhelm Haller, Ulrich Krauch, Kurt Lind, Friedrich Schroeder, Alexander Woerner
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Patent number: 8516417Abstract: The invention relates to a method and a system for repartitioning a formalized hardware description of a hierarchically structured electronic circuit design unit comprising a plurality of macros in terms of latch macros and combinatorial macros. In a first step, each macro is dissected into latch macros and signal cones in such a way that each signal cone comprises signals linking macro input/output to a latch output/input, and each latch macro comprises at least one latch, each primary input an output of said latch macro coinciding with an input or an output of a latch within said latch macro. Subsequently, combinatorial macros are created by merging combinatorial signal cones along unit signal paths.Type: GrantFiled: July 7, 2010Date of Patent: August 20, 2013Assignee: International Business Machines CorporationInventors: Elmar Gaugler, Wilhelm Haller, Friedhelm Kessler
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Patent number: 8423940Abstract: A computerized method, data processing system and computer program product reduce noise for a buffered design of an electronic circuit which was already placed and routed. For all areas between a power stripe and a ground stripe (half bay) in the design, the shapes are divided in different criticality levels. The shapes are rearranged based on their criticality level such that shapes with higher criticality level are placed closer to the stripes than those with lower criticality level.Type: GrantFiled: August 15, 2011Date of Patent: April 16, 2013Assignee: International Business Machines CorporationInventors: Lukas Daellenbach, Elmar Gaugler, Wilhelm Haller, Ralf Richter