Patents by Inventor Wilhelm Haller
Wilhelm Haller has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20130047130Abstract: A computerized method, data processing system and computer program product reduce noise for a buffered design of an electronic circuit which was already placed and routed. For all areas between a power stripe and a ground stripe (half bay) in the design, the shapes are divided in different criticality levels. The shapes are rearranged based on their criticality level such that shapes with higher criticality level are placed closer to the stripes than those with lower criticality level.Type: ApplicationFiled: August 15, 2011Publication date: February 21, 2013Applicant: IBM CORPORATIONInventors: Lukas Daellenbach, Elmar Gaugler, Wilhelm Haller, Ralf Richter
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Patent number: 8302056Abstract: The invention relates to a method and a system for placing macros of a multilevel hierarchical description of a design unit on a chip. The method starts off by repartitioning the macro structure of the design unit into a set of latch macros and a set of combinatorial macros. By definition, a combinatorial macro is constructed in such a way that it contains no latches, and a latch macro contains latches and is constructed in such a way that each primary input/output of the latch macro coincides with an input or an output of a latch within said latch macro. After repartitioning the macro structure, the latch macros are synthesized within temporary boundaries and placed on the chip. Subsequently, the combinatorial macros are sequentially placed within a temporary boundary and synthesized one by one.Type: GrantFiled: July 7, 2010Date of Patent: October 30, 2012Assignee: International Business Machines CorporationInventors: Elmar Gaugler, Wilhelm Haller, Friedhelm Kessler
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Patent number: 8286115Abstract: A system for creating layout and wiring diagrams for an integrated circuit (IC) includes a placement engine configured to receive a hierarchical schematic and to create a placed layout. The system also includes a flat layout engine configured to receive the hierarchical schematic and to create a flat layout and a back annotation engine coupled to the placement engine and the flat layout engine, the back annotation engine configured to receive the hierarchical placed layout and the flat unplaced layout and to create a flat placed layout there from.Type: GrantFiled: December 9, 2008Date of Patent: October 9, 2012Assignee: International Business Machines CorporationInventors: Holger Wetter, Maarten Boersma, Wilhelm Haller, Armin Windschiegl
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Patent number: 8086657Abstract: A digital adder circuit comprising a plurality of logical stages in the carry logic of said adder circuit, for generating and propagating predetermined groups of operand bits, each stage implementing a predetermined logic function and processing input variables from a preceding stage and outputting result values to a succeeding stage static and dynamic logic in the carry network of a 4-bit adder, and with output from the first stage fed directly as an input (60, 62) to the third stage of the carry network. Preferably, stages having normally relatively high switching activities are implemented in static logic. Preferably, the first stage of its carry network is implemented in a static logic, and the rest of the stages in dynamic logic.Type: GrantFiled: April 9, 2008Date of Patent: December 27, 2011Assignee: International Business Machines CorporationInventors: Wilhelm Haller, Rolf Sautter, Christoph Wandel, Ulrich Weiss
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Patent number: 7908308Abstract: A Carry-Select Adder structure comprising a carry generation network and a multiplexer to select a particular pre-calculatad sum of a bit-group via orthogonal signal levels of a Hot-Carry signal provided by said carry generation network (21), wherein in order to provide orthogonal signal levels of said Hot-Carry signal, the carry generation network (21) comprises two carry lookahead trees (22, 23) working in parallel to each other, wherein a first carry lookahead tree (22) provides a first signal level of the Hot-Carry signal, and a second carry lookahead tree (23) provides a second, compared to the first signal level inverse signal level of the Hot-Carry signal. Furthermore a method to operate such a Carry-Select Adder is described.Type: GrantFiled: May 15, 2007Date of Patent: March 15, 2011Assignee: International Business Machines CorporationInventors: Wilhelm Haller, Mark Mayo, Ricardo H. Nigaglioni, Hartmut Sturm
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Publication number: 20110035712Abstract: The invention relates to a method and a system for placing macros of a multilevel hierarchical description of a design unit on a chip. The method starts off by repartitioning the macro structure of the design unit into a set of latch macros and a set of combinatorial macros. By definition, a combinatorial macro is constructed in such a way that it contains no latches, and a latch macro contains latches and is constructed in such a way that each primary input/output of the latch macro coincides with an input or an output of a latch within said latch macro. After repartitioning the macro structure, the latch macros are synthesized within temporary boundaries and placed on the chip. Subsequently, the combinatorial macros are sequentially placed within a temporary boundary and synthesized one by one.Type: ApplicationFiled: July 7, 2010Publication date: February 10, 2011Applicant: International Business Machines CorporationInventors: Elmar Gaugler, Wilhelm Haller, Friedhelm Kessler
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Publication number: 20110035711Abstract: The invention relates to a method and a system for repartitioning a formalized hardware description of a hierarchically structured electronic circuit design unit comprising a plurality of macros in terms of latch macros and combinatorial macros. In a first step, each macro is dissected into latch macros and signal cones in such a way that each signal cone comprises signals linking macro input/output to a latch output/input, and each latch macro comprises at least one latch, each primary input an output of said latch macro coinciding with an input or an output of a latch within said latch macro. Subsequently, combinatorial macros are created by merging combinatorial signal cones along unit signal paths.Type: ApplicationFiled: July 7, 2010Publication date: February 10, 2011Applicant: International Business Machines CorporationInventors: Elmar Gaugler, Wilhelm Haller, Friedhelm Kessler
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Publication number: 20100146471Abstract: A system for creating layout and wiring diagrams for an integrated circuit (IC) includes a placement engine configured to receive a hierarchical schematic and to create a placed layout. The system also includes a flat layout engine configured to receive the hierarchical schematic and to create a flat layout and a back annotation engine coupled to the placement engine and the flat layout engine, the back annotation engine configured to receive the hierarchical placed layout and the flat unplaced layout and to create a flat placed layout there from.Type: ApplicationFiled: December 9, 2008Publication date: June 10, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Holger Wetter, Maarten Boersma, Wilhelm Haller, Armin Windschiegl
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Patent number: 7546565Abstract: A method implemented as a computer program product for comparing two designs of electronic circuits, wherein the design representations comprise several hierarchically related sheets. The method comprises the steps of (a) identifying corresponding top-sheets of the first hierarchy level in the design versions; (b) generating a list of all sub-sheets for each top-sheet and comparing the lists to identify added, removed and common sheets of the corresponding top-sheets; (c) defining the common sheets as corresponding top-sheets of a next hierarchy level; and (d) repeating steps (a)-(c) until at least one of the top-sheets does not comprise any sub-sheet.Type: GrantFiled: January 11, 2007Date of Patent: June 9, 2009Assignee: International Business Machines CorporationInventors: Joachim Fenkes, Wilhelm Haller, Tobias Werner, Alexander Woerner
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Patent number: 7530038Abstract: According to the present invention a method for the placement of electronic circuit components is provided that supports design modifications by realizing and maintaining relations between the layouts of the components (i1 to i6). These relations are based on relations between the geometrical shapes represented by the layouts for the components. The invention can be implemented by an interactive layout editor. When a layout or the placement of a layout is changed manually, then the placement of the components that are placed already is changed automatically such that the all the relations between the components are realized or maintained. A parent-child relationship can be defined between components such that when the parent component is changed or moved then only the placement of its children is updated automatically. The prioritisation of relations allows resolving conflicts between conflicting relations.Type: GrantFiled: September 8, 2006Date of Patent: May 5, 2009Assignee: International Business Machines CorporationInventors: George D. Gristede, Wilhelm Haller, Friedhelm Kessler, Matthias Klein
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Publication number: 20090112963Abstract: A method, circuit apparatus, and a design structure on which the circuit resides, is provided to perform a subtraction of two operands in a binary arithmetic unit by subdividing two operands into groups of equal numbers of bits, generating, by appropriate arithmetic operations, pairs of intermediate results for the particular groups of bits of the two operands comprising the same bit positions, respectively. A first intermediate result of each pair of intermediate results is generated under the assumption of a carry-in of ‘0’ and a second intermediate result of each pair of intermediate results is generated under the assumption of a carry-in of ‘1’. The correct intermediate result of each particular pair of intermediate results from each group of bits is selected, and the result of the subtraction of the two operands is generated by an appropriate merging of the selected correct intermediate results.Type: ApplicationFiled: October 29, 2007Publication date: April 30, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Wilhelm Haller, Guenter Mayer, Veit Gernhoefer, Ulrich Krauch, Simon Fabel
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Publication number: 20080294706Abstract: A digital adder circuit comprising a plurality of logical stages in the carry logic of said adder circuit, for generating and propagating predetermined groups of operand bits, each stage implementing a predetermined logic function and processing input variables from a preceding stage and outputting result values to a succeeding stage static and dynamic logic in the carry network of a 4-bit adder, and with output from the first stage fed directly as an input (60, 62) to the third stage of the carry network. Preferably, stages having normally relatively high switching activities are implemented in static logic. Preferably, the first stage of its carry network is implemented in a static logic, and the rest of the stages in dynamic logic.Type: ApplicationFiled: April 9, 2008Publication date: November 27, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Wilhelm Haller, Rolf Sautter, Christoph Wandel, Ulrich Weiss
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Patent number: 7406495Abstract: A digital adder circuit comprising a plurality of logical stages in the carry logic of said adder circuit, for generating and propagating predetermined groups of operand bits, each stage implementing a predetermined logic function and processing input variables from a preceding stage and outputting result values to a succeeding stage with static and dynamic logic in the carry network of a 4-bit adder, and with output from the first stage fed directly as an input (60, 62) to the third stage of the carry network. Preferably, stages having normally relatively high switching activities are implemented in static logic. Preferably, the first stage of its carry network is implemented in a static logic, and the rest of the stages in dynamic logic.Type: GrantFiled: October 26, 2004Date of Patent: July 29, 2008Assignee: International Business Machines CorporationInventors: Wilhelm Haller, Rolf Sautter, Christoph Wandel, Ulrich Weiss
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Publication number: 20080177816Abstract: A method to generate a magnitude result of a mathematic operation of two decimal operands within one cycle in a decimal arithmetic logic unit structure, wherein the decimal operands are in hexadecimal sign magnitude format.Type: ApplicationFiled: January 14, 2008Publication date: July 24, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Wilhelm Haller, Ulrich Krauch, Guenter Mayer, Eric M. Schwarz
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Publication number: 20080172640Abstract: A method for comparing two designs of electronic circuits, especially for comparing different versions of a design for an electronic circuit, wherein the design representations comprise several hierarchically related sheets. The method comprises the steps of: a) analyzing the hierarchies of said design versions to identify added, removed and common sheets; b) determining differences between common sheets to identify modified sheets; and c) visualizing the combined hierarchies of said design versions wherein added, removed and modified sheets are marked.Type: ApplicationFiled: January 11, 2007Publication date: July 17, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Joachim Fenkes, Wilhelm Haller, Tobias Werner, Alexander Woerner
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Publication number: 20080071852Abstract: A method and apparatus is provided to perform a subtraction of two operands in a binary arithmetic unit by subdividing two operands into groups of equal numbers of bits, generating, by appropriate arithmetic operations, pairs of intermediate results for the particular groups of bits of the two operands comprising the same bit positions, respectively. A first intermediate result of each pair of intermediate results is generated under the assumption of a carry-in of ‘0’ and a second intermediate result of each pair of intermediate results is generated under the assumption of a carry-in of ‘1’. The correct intermediate result of each particular pair of intermediate results from each group of bits is selected, and the result of the subtraction of the two operands is generated by an appropriate merging of the selected correct intermediate results.Type: ApplicationFiled: September 14, 2007Publication date: March 20, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Wilhelm Haller, Guenter Mayer, Veit Gernhoefer, Ulrich Krauch, Simon Fabel
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Publication number: 20080046498Abstract: A Carry-Select Adder structure comprising a carry generation network and a multiplexer to select a particular pre-calculatad sum of a bit-group via orthogonal signal levels of a Hot-Carry signal provided by said carry generation network (21), wherein in order to provide orthogonal signal levels of said Hot-Carry signal, the carry generation network (21) comprises two carry lookahead trees (22, 23) working in parallel to each other, wherein a first carry lookahead tree (22) provides a first signal level of the Hot-Carry signal, and a second carry lookahead tree (23) provides a second, compared to the first signal level inverse signal level of the Hot-Carry signal. Furthermore a method to operate such a Carry-Select Adder is described.Type: ApplicationFiled: May 15, 2007Publication date: February 21, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Wilhelm Haller, Mark Mayo, Ricardo H. Nigaglioni, Hartmut Sturm
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Patent number: 7224190Abstract: The present invention relates to the field of hardware logic circuits and in particular to dynamic hardware logic implemented in computer processors, and more particularly, to an integrated circuit comprising a dynamic logic function implementing a predetermined logic function with a plurality of transistor stacks, the integrated circuit comprising a precharge node at the input of said logic function implementation, an output latch connected to the output node of said logic function for stabilizing the result of the evaluation of said logic function. The present invention provides such integrated dynamic circuit with a latch, which is protected against instability even in situations involving complex logic functions which are evaluated and their output states are saved by said output latch.Type: GrantFiled: December 10, 2004Date of Patent: May 29, 2007Assignee: International Business Machines CorporationInventors: Wilhelm Haller, Rolf Sautter, Monika Strohmer, Klaus Thumm
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Publication number: 20070083837Abstract: According to the present invention a method for the placement of electronic circuit components is provided that supports design modifications by realizing and maintaining relations between the layouts of the components (i1 to i6). These relations are based on relations between the geometrical shapes represented by the layouts for the components. The invention can be implemented by an interactive layout editor. When a layout or the placement of a layout is changed manually, then the placement of the components that are placed already is changed automatically such that the all the relations between the components are realized or maintained. A parent-child relationship can be defined between components such that when the parent component is changed or moved then only the placement of its children is updated automatically. The prioritisation of relations allows resolving conflicts between conflicting relations.Type: ApplicationFiled: September 8, 2006Publication date: April 12, 2007Inventors: George Gristede, Wilhelm Haller, Friedhelm Kessler, Matthias Klein
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Charge sharing reduction by applying intrinsic parallelism in complex dynamic domino type CMOS gates
Patent number: 7095252Abstract: The present invention relates to dynamic hardware logic of computer processors. In particular, it relates to a method and respective system for operating a dynamic logic circuit implementing some predetermined logic function with reduced charge sharing. In order to further reduce charge sharing it is proposed to provide a predetermined number of pre-engineered switching arrangements (24, 26, 28) implementing the same logic function with a different combinatorial distribution of input variables (A, B, C), wherein each arrangement is connected between said precharged node of higher potential and a lower potential.Type: GrantFiled: July 22, 2004Date of Patent: August 22, 2006Assignee: International Business Machines CorporationInventors: Michael Haase, Wilhelm Haller, Rolf Sautter, Christoph Wandel