Abstract: A system for performing decimal floating point addition. The system includes input registers for inputting a first and second operand for an addition operation. The system also includes a plurality of adder blocks, each calculating a sum of one or more corresponding digits from the first operand and the second operand. Output from each of the adder blocks includes the sum of the corresponding digits and a carry out indicator for the corresponding digits. The calculating is performed during a first clock cycle. The system also includes an intermediate result register for storing the sums of the corresponding digits output from each of the plurality of adder blocks, the storing during the first clock cycle. The system further includes a carry chain for storing the carry out indicator output from each of the plurality of adder blocks, the storing occurring during the first clock cycle.

Abstract: An adder circuit for adding two binary or two decimal operands A and B in which the carries are calculated directly from the input operands A and B without including the plus 6 or minus 6 operations into the carry calculation. For all timing critical functions the reduced input data set, i.e., valid decimal data can be used and the non-existing decimal numbers (10 to 15) need not be excluded by separate check logic any more. This reduces the complexity of the logic functions.

Abstract: The present invention relates to computer processors. In particular it relates to a method and respective system for operating a digital adder circuit comprising a plurality of logical stages in the carry logic of said adder circuit, for generating and propagating predetermined groups of operand bits, each stage implementing a predetermined logic function and processing input variables from a preceding stage and outputting result values to a succeeding stage. In order to reduce power consumption of adders and concurrently increasing adder speed it is proposed to implement a mixture of static and dynamic logic in the carry network of a 4-bit adder, and to feed output from the first stage directly as an input (60, 62) to the third stage of the carry network. Preferably, stages having normally relatively high switching activities are implemented in static logic. Preferably, the first stage of its carry network is implemented in a static logic, and the rest of the stages in dynamic logic.

Abstract: The present invention relates to the field of hardware logic circuits and in particular to dynamic hardware logic implemented in computer processors, and more particularly, to an integrated circuit comprising a dynamic logic function implementing a predetermined logic function with a plurality of transistor stacks, the integrated circuit comprising a precharge node at the input of said logic function implementation, an output latch connected to the output node of said logic function for stabilizing the result of the evaluation of said logic function. The present invention provides such integrated dynamic circuit with a latch, which is protected against instability even in situations involving complex logic functions which are evaluated and their output states are saved by said output latch.

Abstract: The present invention relates to dynamic hardware logic of computer processors. In particular, it relates to a method and respective system for operating a dynamic logic circuit implementing some predetermined logic function with reduced charge sharing. In order to further reduce charge sharing it is proposed to provide a predetermined number of pre-engineered switching arrangements (24, 26, 28) implementing the same logic function with a different combinatorial distribution of input variables (A, B, C), wherein each arrangement is connected between said precharged node of higher potential and a lower potential.

Abstract: A binary and decimal adder unit uses a pre-sum logic for generating pre-sums of the operands A, B under the presumption of one and zero carry inputs into the decimal digit position, and also uses a digits carry network for generating binary carries within the decimal digit positions and a high order carry out signal of said plurality of decimal digits. Each decimal digit position of said adder unit provides a six correction and a pre-sum selection. The pre-sum logic comprises a carry prediction logic for generating decimal digit position carry out signals on the presumption of a zero carry input and of a one carry input into the decimal digit.

Abstract: A shifting structure and method which separates a shifting operation into partial shifts which may be executed in different pipeline staged is described herein. In a first pipe stage, an operand is read out and at least one partial shift is accomplished by placing the operand or parts thereof into registers coupled to a shift unit. The shift unit, in a second pipe stage, finalizes the shifting operation executing the remaining partial shifts, thereby reducing the time required for the total shifting operation. A control string is derived in the shift unit based on the shift amount to correct the output of the shifted result as well as providing for parity prediction therefor.

Abstract: One or more processing units are connected with a clock component (comprising a clock) over a bi-directional serial link, and data frames are transmitted between the clock component and the processing units. The clock component may contain a serial link combination circuit for combining multiple processing unit serial links, operating in parallel, into a single serial link connected to the clock. Both of the clock component and the processing units contain an error detection and correction mechanism which examine and modify data within the data frames to perform error detection and correction. The clock component optionally contains an external interface for connection to a command-issuing Service Processor.

Abstract: A combined adder and logic unit having a reduced operation delay of arithmetic and logic operations, and providing an improved fan in and reduced wiring delays and capacity if implemented in the arithmetic and logic section of a microprocessor chip. The unit comprises a carry network (30) connected to operand inputs for generating carry-out signals of the byte positions (By0-By7) and further comprises a pre-sum logic (32) having a bit function generator (42) and a sum generator (45, 46, 48). Said bit function generator derives from the operands Ai and Bi bit functions Gi, Pi which are provided as logic function output and as input to said sum generator for producing preliminary arithmetic functions (SUM0, SUM1) to anticipate carry-in signals of one or zero.

Abstract: A combined binary/decimal adder unit reduces the operation delay ine processing binary coded decimal operands and permit an increased cycle rate of a processor unit in which the combined binary/decimal adder unit is utilized. Pre-sums are generated for each decimal digit position in parallel to the generation and distribution of the carries over the total of decimal digit positions of the adder unit. The pre-sums anticipate the carry-in of the decimal positions and the need to perform six corrections after the carry-out signal of the highest decimal digit position has been generated. The carry-out signal of each decimal digit position is used in combination with operation control signals to select the correct pre-sum of the digit position.

Abstract: A method and apparatus for the determination of leading zero digits of a sum is presented herein. The technique incorporates the parallel determination of partial sums of single digits accounting for the possibility of carries and on the basis thereof the pre-determination of potential zero digits or potential leading zero digits. Upon the establishment of a correct partial sum, the potential zero digits are selected and evaluated thereby determining the leading zero digits. The invention may be implemented in an adder in parallel or via a hierarchical structure. The parallelism permits time-savings in the determination of a normalized sum. The invention is preferably incorporated into adders, floating point computing units and/or data processing units.

Abstract: A method and system for executing branch or other instructions in a loop. A loop end condition is evaluated in a fixed point unit while floating point instructions are evaluated in a floating point unit. In a first execution of the instructions in the loop, the loop end condition is processed as in prior art. A branch target instruction is stored in a branch target register and an instruction address of the branch target instruction is stored in a branch address register. However, on subsequent execution of the instructions in the loop, the branch condition is evaluated and, if it is fulfilled, once the end of the loop is detected by comparison of the effective address of the next instruction to be executed with the contents of the branch address register, the effective address of the first instruction in the loop is passed from the branch target register to an operations register.

Abstract: A method of operating a timer mechanism in a digital data processing system is described in which the contents of at least one timer register is updated by a predetermined time increment during each of successive periodic update cycles. Each update cycle includes a predetermined number of operating cycles of the data processing system. During each update cycle, the contents of an adjustment register is circularly shifted by one bit position and if the bit value at a particular position in this adjustment register has a predetermined binary value during an update cycle, then actual updating of the timer register is omitted during a related update cycle.