Patents by Inventor Willem Frederik Adrianus Besling

Willem Frederik Adrianus Besling has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method of manufacturing a semiconductor device
    Patent number: 6562732
    Abstract: The invention relates to a method of manufacturing a semiconductor device, comprising the provision of a dual damascene structure (20). This dual damascene structure (20) comprises a metal layer (1) with thereon a first dielectric layer (2) provided with a via (3). A second dielectric layer (5) is applied on the first dielectric layer (2) and is provided with an interconnect groove (6). The via (3) and the interconnect groove (6) are filled with a metal which forms a metal lead (9) with a top (10). The method further comprises the following steps: removing the second dielectric layer (5), applying a disposable layer (12) to the first dielectric layer (2) and the metal lead (9), planarizing the disposable layer (12) down to the top (10) of the metal lead (9), applying a porous dielectric layer (13) on the disposable layer (12), removing the disposable layer (12) through the porous dielectric layer (13) so as to form air gaps (14).
    Type: Grant
    Filed: August 30, 2001
    Date of Patent: May 13, 2003
    Assignee: Koninklijke Philips Electronics N.V.
    Inventors: Willem Frederik Adrianus Besling, Cornelis Adrianus Henricus Antonius Mutsaers, Dirk Jan Gravesteijn
  • Method of manufacturing a semiconductor device
    Publication number: 20020028575
    Abstract: The invention relates to a method of manufacturing a semiconductor device, comprising the provision of a dual damascene structure (20). This dual damascene structure (20) comprises a metal layer (1) with thereon a first dielectric layer (2) provided with a via (3). A second dielectric layer (5) is applied on the first dielectric layer (2) and is provided with an interconnect groove (6). The via (3) and the interconnect groove (6) are filled with a metal which forms a metal lead (9) with a top (10).
    Type: Application
    Filed: August 30, 2001
    Publication date: March 7, 2002
    Applicant: KONINKLIJKE PHILIPS ELECTRONICS N.V.
    Inventors: Willem Frederik Adrianus Besling, Cornelis Adrianus Henricus Antonius Mutsaers, Dirk Jan Gravesteijn