Abstract: A crossbar switch with primary and secondary pickers is described herein. The crossbar switch includes a crossbar switch command scheduler that schedules commands that are to be routed across the crossbar from multiple source ports to multiple destination ports. The crossbar switch command scheduler uses primary and secondary pickers to schedule two commands per clock cycle. The crossbar switch may also include a dedicated response bus, a general purpose bus and a dedicated command bus. A system request interface may include dedicated command and data packet buffers to work with the primary and secondary pickers.

Abstract: A data processing device is disclosed that includes multiple processing cores, where each core is associated with a corresponding cache. When a processing core is placed into a first sleep mode, the data processing device initiates a first phase. If any cache probes are received at the processing core during the first phase, the cache probes are serviced. At the end of the first phase, the cache corresponding to the processing core is flushed, and subsequent cache probes are not serviced at the cache. Because it does not service the subsequent cache probes, the processing core can therefore enter another sleep mode, allowing the data processing device to conserve additional power.

Abstract: A method and apparatus for a selectively bypassing a cache in a processor of a computing device are disclosed.

Abstract: The present invention is a system that receives data in different formats from different devices/applications in the format native to the devices/applications and fuses the data into a common shared audio/video collaborative environment including a composite display showing the data from the different sources in different areas of the display and composite audio. The common environment is presented to users who can be at remote locations. The users are allowed to supply a control input for the different device data sources and the control input is mapped back to the source, thereby controlling the source. The location of the control input on the remote display is mapped to the storage area for that portion of the display and the control data is transmitted to the corresponding device/application.

Abstract: A probe for measurement of water temperature profiles is disclosed herein. In various aspects, the probe may include an electronic assembly and a housing over-molded upon at least portions of the electronic assembly to sealingly enclose the portions of the electronic assembly. The electronic assembly may include a pressure sensor to measure a pressure value indicative of a water depth, and a temperature sensor to measure a water temperature value indicative of a water temperature, a communication interface. Methods of manufacture of the probe are also disclosed herein.

Abstract: A system and method for managing multiple discrete operating points to create a stable virtual operating point. One or more functional blocks within a processor produces data corresponding to an activity level associated with the respective functional block. A power manager determines a power consumption value based on the data once every given sample interval. In addition, the power manager determines a signed accumulated difference over time between a thermal design power (TDP) and the power consumption value. The power manager selects a next power-performance state (P-state) based on comparisons of the signed accumulated difference and given thresholds. Transitioning between P-states in this manner while the workload does not significantly change causes the processor to operate at a virtual operating point between supported discrete operating points.

Abstract: In one embodiment, a node comprises a plurality of processor cores and a node controller configured to receive a first read operation addressing a first register. The node controller is configured to return a first value in response to the first read operation, dependent on which processor core transmitted the first read operation. In another embodiment, the node comprises the processor cores and the node controller. The node controller comprises a queue shared by the processor cores. The processor cores are configured to transmit communications at a maximum rate of one every N clock cycles, where N is an integer equal to a number of the processor cores. In still another embodiment, a node comprises the processor cores and a plurality of fuses shared by the processor cores. In some embodiments, the node components are integrated onto a single integrated circuit chip (e.g. a chip multiprocessor).

Abstract: This application describes a system that captures 3D geometry commands from a first 3D graphics process and stores them in a shared memory. A second 3D environment process creates a 3D display environment using a display and display hardware. A third process obtains the 3D commands and supplies them to the hardware to place 3D objects in the 3D environment. The result is a fused display environment where 3D objects are displayed along with other display elements. Input events in the environment are analyzed and mapped to the 3D graphics process or the environment where they affect corresponding processing.

Abstract: In one embodiment, a node comprises a plurality of processor cores and a node controller configured to receive a first read operation addressing a first register. The node controller is configured to return a first value in response to the first read operation, dependent on which processor core transmitted the first read operation. In another embodiment, the node comprises the processor cores and the node controller. The node controller comprises a queue shared by the processor cores. The processor cores are configured to transmit communications at a maximum rate of one every N clock cycles, where N is an integer equal to a number of the processor cores. In still another embodiment, a node comprises the processor cores and a plurality of fuses shared by the processor cores. In some embodiments, the node components are integrated onto a single integrated circuit chip (e.g. a chip multiprocessor).

Abstract: In an embodiment, a node comprises a packet scheduler configured to schedule packets to be transmitted on a link and an interface circuit coupled to the packet scheduler and configured to transmit the packets on the link. The interface circuit is configured to generate error detection data covering the packets, wherein the error detection data is transmitted between packets on the link. The interface circuit is configured to cover up to N packets with one transmission of error detection data, where N is an integer >=2. The number of packets covered with one transmission of error detection data is determined by the interface circuit dependent on an availability of packets to transmit. In another embodiment, the interface circuit is configured to dynamically vary a frequency of transmission of the error detection data on the link based on an amount of bandwidth being consumed on the link.

Abstract: In one embodiment, a method comprises assigning a unique node number to each of a first plurality of nodes in a first partition of a system and a second plurality of nodes in a second partition of the system. A first memory address space spans first memory included in the first partition and a second memory address space spans second memory included in the second partition. The first memory address space and the second memory address space are generally logically distinct. The method further comprises programming a first address map in the first partition to map the first memory address space to node numbers, wherein the programming comprises mapping a first memory address range within the first memory address space to a first node number assigned to a first node of the second plurality of nodes in the second partition, whereby the first memory address range is mapped to the second partition.

Abstract: The present invention is a system that receives data in different formats from different devices/applications in the format native to the devices/applications and fuses the data into a common shared audio/video collaborative environment including a composite display showing the data from the different sources in different areas of the display and composite audio. The common environment is presented to users who can be at remote locations. The users are allowed to supply a control input for the different device data sources and the control input is mapped back to the source, thereby controlling the source. The location of the control input on the remote display is mapped to the storage area for that portion of the display and the control data is transmitted to the corresponding device/application.

Abstract: The present invention is a system that grids original data, maps the data at the grid locations to height values at corresponding landscape image pixel locations and renders the landscape pixels into a three-dimensional (3D) landscape image. The landscape pixels can have arbitrary shapes and can be augmented with additional 3D information from the original data, such as an offset providing additional information, or generated from processing of the original data, such as to alert when a threshold is exceeded, or added for other purposes such as to point out a feature. The pixels can also convey additional information from the original data using other pixel characteristics such as texture, color, transparency, etc.

Abstract: A system includes a processor coupled to a memory through a memory controller. The memory controller includes first and second queues. The memory controller receives memory requests from the processor, assigns a priority to each request, stores each request in the first queue, and schedules processing of the requests based on their priorities. The memory controller changes the priority of a request in the first queue in response to a trigger, sends a next scheduled request from the first queue to the second queue in response to detecting the next scheduled request has the highest priority of any request in the first queue, and sends requests from the second queue to the memory. The memory controller changes the priority of different types of requests in response to different types of triggers. The memory controller maintains a copy of each request sent to the second queue in the first queue.

Abstract: This application describes a system that captures 3D geometry commands from a first 3D graphics process and stores them in a shared memory. A second 3D environment process creates a 3D display environment using a display and display hardware. A third process obtains the 3D commands and supplies them to the hardware to place 3D objects in the 3D environment. The result is a fused display environment where 3D objects are displayed along with other display elements. Input events in the environment are analyzed and mapped to the 3D graphics process or the environment where they affect corresponding processing.

Abstract: A method and mechanism for managing requests to a resource. A request queue receives requests from multiple requestors and maintains a status for each requestor indicating how many requests the requestor has permission to issue. Upon initialization, the request queue allots to each requestor a predetermined number of “hard” entries, and a predetermined number of “free” entries. Un-allotted entries are part of a free pool of entries. If a requestor has an available entry, the requestor may submit a request to the request queue. After receiving a request, the request queue may allot a free pool entry to the requestor if the free pool currently has entries available. Upon de-allocation of a queue entry, if the entry corresponds to a hard entry, then the hard entry is re-allotted to the same requestor. If the entry is a free entry, the entry is made available and a free pool counter is incremented.

Abstract: In one embodiment, a node comprises a plurality of processor cores and a node controller configured to receive a first read operation addressing a first register. The node controller is configured to return a first value in response to the first read operation, dependent on which processor core transmitted the first read operation. In another embodiment, the node comprises the processor cores and the node controller. The node controller comprises a queue shared by the processor cores. The processor cores are configured to transmit communications at a maximum rate of one every N clock cycles, where N is an integer equal to a number of the processor cores. In still another embodiment, a node comprises the processor cores and a plurality of fuses shared by the processor cores. In some embodiments, the node components are integrated onto a single integrated circuit chip (e.g. a chip multiprocessor).

Abstract: In an embodiment, a node comprises a packet scheduler configured to schedule a packet to be transmitted on the link, the packet comprising a command and associated packet data. Coupled to the packet scheduler and configured to transmit the packet on the link, and interface circuit is configured to generate error detection data covering the packet. The interface circuit is configured to transmit the error detection data covering the packet at an end of the packet, and is further configured to insert at least one partial error detection data within the packet. The partial error detection data covers a portion of the packet that precedes the partial error detection data. A receiver is configured to receive the data and forward the data based on partial CRC check.

Abstract: The present invention is a system that grids original data, maps the data at the grid locations to height values at corresponding landscape image pixel locations and renders the landscape pixels into a three-dimensional (3D) landscape image. The landscape pixels can have arbitrary shapes and can be augmented with additional 3D information from the original data, such as an offset providing additional information, or generated from processing of the original data, such as to alert when a threshold is exceeded, or added for other purposes such as to point out a feature. The pixels can also convey additional information from the original data using other pixel characteristics such as texture, color, transparency, etc.

Abstract: The present invention is a system that receives data in different formats from different devices/applications in the format native to the devices/applications and fuses the data into a common shared audio/video collaborative environment including a composite display showing the data from the different sources in different areas of the display and composite audio. The common environment is presented to users who can be at remote locations. The users are allowed to supply a control input for the different device data sources and the control input is mapped back to the source, thereby controlling the source. The location of the control input on the remote display is mapped to the storage area for that portion of the display and the control data is transmitted to the corresponding device/application.