Patents by Inventor William E. Bernier
William E. Bernier has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230105420Abstract: A computer readable barcode on a surface of a corrodible material, and method of forming. A surface depression of an inverse bar code pattern is etched or engraved within the surface and around the code elements. A corrosion-resistant material is cured within the surface depression formed by the engraving. The corrosion-resistant material is lightly colored to frame the formed barcode lines.Type: ApplicationFiled: October 3, 2022Publication date: April 6, 2023Applicant: Operations Technology Development, NFPInventors: William Gale, Kenneth Skorenko, William E. Bernier
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Publication number: 20200316577Abstract: Mixed-phase TiO2 nanofibers prepared via a sol-gel technique followed by electrospinning and calcination are provided as photocatalysts. The calcination temperature is adjusted to control the rutile phase fraction in TiO2 nanofibers relative to the anatase phase. Post-calcined TiO2 nanofibers composed of 38 wt % rutile and 62 wt % anatase exhibited the highest initial rate constant of UV photocatalysis. This can be attributed to the combined influences of the fibers' specific surface areas and their phase compositions.Type: ApplicationFiled: May 26, 2020Publication date: October 8, 2020Inventors: Wayne E. Jones, Jian Liu, William E. Bernier, Julia B. Tollin, Danielle McCarthy, Emilly Obuya, Jared DeCoste
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Patent number: 10699972Abstract: A symmetrical, flat laminate structure used to minimize variables in a test structure to experimentally gauge white bump sensitivity to CTE mismatch is disclosed. The test structure includes a flat laminate structure. The method of using the test structure includes isolating a cause of a multivariable chip join problem that is adversely impacted by warpage and quantifying a contribution of the warpage, itself, in a formation of the multivariable chip join problem.Type: GrantFiled: November 30, 2017Date of Patent: June 30, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: William E. Bernier, Timothy H. Daubenspeck, Virendra R. Jadhav, Valerie A. Oberson, David L. Questad
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Patent number: 10661261Abstract: Mixed-phase TiO2 nanofibers prepared via a sol-gel technique followed by electrospinning and calcination are provided as photocatalysts. The calcination temperature is adjusted to control the rutile phase fraction in TiO2 nanofibers relative to the anatase phase. Post-calcined TiO2 nanofibers composed of 38 wt % rutile and 62 wt % anatase exhibited the highest initial rate constant of UV photocatalysis. This can be attributed to the combined influences of the fibers' specific surface areas and their phase compositions.Type: GrantFiled: March 14, 2016Date of Patent: May 26, 2020Assignees: The Research Foundation For The State University of New York, LEIDOS, Inc.Inventors: Wayne E. Jones, Jian Liu, William E. Bernier, Julia B. Tollin, Danielle McCarthy, Emilly Obuya, Jared DeCoste
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Patent number: 10459121Abstract: Compositions for increasing the thermal stability of optical absorbers are provided as well as methods of making and using the resulting compositions. The compositions or complexes of the present teachings generally include an optical absorber bound to a metal or a metal oxide through one or more linkers, which contain a metal binding moiety.Type: GrantFiled: July 31, 2017Date of Patent: October 29, 2019Assignees: The Research Foundation for the State University of New York, Crysta-Lyn Chemical Company, Inc.Inventors: William E. Bernier, Megan Fegley, Bradley Galusha, Francis D. Goroleski, Wayne E. Jones, Kenneth H. Skorenko
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Publication number: 20180350768Abstract: A interposer sandwich structure comprises a top interposer and a bottom interposer enclosing an integrated circuit electronic device that includes means for attaching the device to the bottom interposer, and an interconnection structure connecting the top interposer to the bottom interposer. The top interposer may also be directly connected to a chip carrier in addition to the bottom interposer. The structure provides shielding and protection of the device against Electrostatic Discharge (ESD), Electromagnetic Interference (EMI), and Electromagnetic Conductivity (EMC) in miniaturized 3D packaging.Type: ApplicationFiled: August 7, 2018Publication date: December 6, 2018Applicant: International Business Machines CorporationInventors: William E. BERNIER, Bing Dang, Mario J. Interrante, John U. Knickerbocker, Son K. Tran
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Publication number: 20180082912Abstract: A symmetrical, flat laminate structure used to minimize variables in a test structure to experimentally gauge white bump sensitivity to CTE mismatch is disclosed. The test structure includes a flat laminate structure. The method of using the test structure includes isolating a cause of a multivariable chip join problem that is adversely impacted by warpage and quantifying a contribution of the warpage, itself, in a formation of the multivariable chip join problem.Type: ApplicationFiled: November 30, 2017Publication date: March 22, 2018Inventors: William E. Bernier, Timothy H. Daubenspeck, Virendra R. Jadhav, Valerie A. Oberson, David L. Questad
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Patent number: 9920220Abstract: Embodiments of films and material layers comprising PEDOT. These embodiments are the result of methods that utilize polymerization processes including vapor phase polymerization (VPP) to form the conductive film comprising PEDOT. In one embodiment, the film can result from a method that includes steps for depositing a coating solution onto a substrate, exposing the substrate to a monomer source, and cleaning the substrate after polymerization. The coating solution can comprise an initiating oxidant, which facilitates growth of PEDOT from 3,4 ethylenedioxythiophene (EDOT), as well as a quenching agent that neutralizes acid that results from polymerization.Type: GrantFiled: March 14, 2014Date of Patent: March 20, 2018Assignee: The Research Foundation of State University of New YorkInventors: William E. Bernier, Nicholas A. Ravvin, Wayne E. Jones, Jr., Kenneth H. Skorenko
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Patent number: 9915757Abstract: Compositions for increasing the thermal stability of optical absorbers are provided as well as methods of making and using the resulting compositions. The compositions or complexes of the present teachings generally include an optical absorber bound to a metal or a metal oxide through one or more linkers, which contain a metal binding moiety.Type: GrantFiled: June 24, 2014Date of Patent: March 13, 2018Assignee: The Research Foundation for the State University of New YorkInventors: William E. Bernier, Megan Fegley, Bradley Galusha, Francis D. Goroleski, Wayne E. Jones, Jr., Kenneth H. Skorenko
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Patent number: 9899279Abstract: A symmetrical, flat laminate structure used to minimize variables in a test structure to experimentally gauge white bump sensitivity to CTE mismatch is disclosed. The test structure includes a flat laminate structure. The method of using the test structure includes isolating a cause of a multivariable chip join problem that is adversely impacted by warpage and quantifying a contribution of the warpage, itself, in a formation of the multivariable chip join problem.Type: GrantFiled: October 17, 2014Date of Patent: February 20, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: William E. Bernier, Timothy H. Daubenspeck, Virendra R. Jadhav, Valerie A. Oberson, David L. Questad
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Publication number: 20170056873Abstract: Mixed-phase TiO2 nanofibers prepared via a sol-gel technique followed by electrospinning and calcination are provided as photocatalysts. The calcination temperature is adjusted to control the rutile phase fraction in TiO2 nanofibers relative to the anatase phase. Post-calcined TiO2 nanofibers composed of 38 wt % rutile and 62 wt % anatase exhibited the highest initial rate constant of UV photocatalysis. This can be attributed to the combined influences of the fibers' specific surface areas and their phase compositions.Type: ApplicationFiled: March 14, 2016Publication date: March 2, 2017Inventors: Wayne E. Jones, Jian Liu, William E. Bernier, Julia B. Tollin, Danielle McCarthy, Emilly Obuya, Jared DeCoste
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Publication number: 20160233190Abstract: A interposer sandwich structure comprises a top interposer and a bottom interposer enclosing an integrated circuit electronic device that includes means for attaching the device to the bottom interposer, and an interconnection structure connecting the top interposer to the bottom interposer. The top interposer may also be directly connected to a chip carrier in addition to the bottom interposer. The structure provides shielding and protection of the device against Electrostatic Discharge (ESD), Electromagnetic Interference (EMI), and Electromagnetic Conductivity (EMC) in miniaturized 3D packaging.Type: ApplicationFiled: April 18, 2016Publication date: August 11, 2016Applicant: International Business Machines CorporationInventors: William E. Bernier, Bing Dang, Mario J. Interrante, John U. Knickerbocker, Son K. Tran
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Patent number: 8957531Abstract: A symmetrical, flat laminate structure used to minimize variables in a test structure to experimentally gauge white bump sensitivity to CTE mismatch is disclosed. The test structure includes a flat laminate structure. The method of using the test structure includes isolating a cause of a multivariable chip join problem that is adversely impacted by warpage and quantifying a contribution of the warpage, itself, in a formation of the multivariable chip join problem.Type: GrantFiled: October 20, 2011Date of Patent: February 17, 2015Assignee: International Business Machines CorporationInventors: William E. Bernier, Timothy H. Daubenspeck, Virendra R. Jadhav, Valerie A. Oberson, David L. Questad
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Publication number: 20150036716Abstract: A symmetrical, flat laminate structure used to minimize variables in a test structure to experimentally gauge white bump sensitivity to CTE mismatch is disclosed. The test structure includes a flat laminate structure. The method of using the test structure includes isolating a cause of a multivariable chip join problem that is adversely impacted by warpage and quantifying a contribution of the warpage, itself, in a formation of the multivariable chip join problem.Type: ApplicationFiled: October 17, 2014Publication date: February 5, 2015Inventors: William E. Bernier, Timothy H. Daubenspeck, Virendra R. Jadhav, Valerie A. Oberson, David L. Questad
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Publication number: 20140272342Abstract: Embodiments of films and material layers comprising PEDOT. These embodiments are the result of methods that utilize polymerization processes including vapor phase polymerization (VPP) to form the conductive film comprising PEDOT. In one embodiment, the film can result from a method that includes steps for depositing a coating solution onto a substrate, exposing the substrate to a monomer source, and cleaning the subsrate after polymerization. The coating solution can comprise an initiating oxidant, which facilitates growth of PEDOT from 3,4 ethylenedioxythiophene (EDOT), as well as a quenching agent that neutralizes acid that results from polymerization.Type: ApplicationFiled: March 14, 2014Publication date: September 18, 2014Applicant: THE RESEARCH FOUNDATION OF STATE UNIVERSITY OF NEW YORKInventors: William E. Bernier, Nicholas A. Ravvin, Wayne E. Jones, JR., Kenneth H. Skorenko
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Patent number: 8444043Abstract: An array of solder balls is attached to solder pads of one of a first substrate and a second substrate. After aligning the array of solder balls relative to solder pads of the other of the first substrate and the second substrate, a thermal-mass-increasing fixture is placed on a surface of the second substrate to form an assembly of the first substrate, the second substrate, and the array of the solder balls therebetween, and the thermal-mass-increasing fixture. The thermal-mass-increasing fixture is in physical contact with at least a surface of a periphery of the second substrate. The thermal-mass-increasing fixture reduces the cool-down rate of peripheral solder balls after a reflow step, thereby increasing time for deformation of peripheral solder balls during the cool-down and reducing the mechanical stress on the solder balls after the cool-down.Type: GrantFiled: January 31, 2012Date of Patent: May 21, 2013Assignee: International Business Machines CorporationInventors: William E. Bernier, Marcus E. Interrante, Rajneesh Kumar, Chenzhou Lian, Janak G. Patel, Peter Slota, Jr.
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Publication number: 20130098176Abstract: A symmetrical, flat laminate structure used to minimize variables in a test structure to experimentally gauge white bump sensitivity to CTE mismatch is disclosed. The test structure includes a flat laminate structure. The method of using the test structure includes isolating a cause of a multivariable chip join problem that is adversely impacted by warpage and quantifying a contribution of the warpage, itself, in a formation of the multivariable chip join problem.Type: ApplicationFiled: October 20, 2011Publication date: April 25, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: William E. Bernier, Timothy H. Daubenspeck, Virendra R. Jadhav, Valerie A. Oberson, David L. Questad
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Publication number: 20130082365Abstract: A interposer sandwich structure comprises a top interposer and a bottom interposer enclosing an integrated circuit electronic device that includes means for attaching the device to the bottom interposer, and an interconnection structure connecting the top interposer to the bottom interposer. The top interposer may also be directly connected to a chip carrier in addition to the bottom interposer. The structure provides shielding and protection of the device against Electrostatic Discharge (ESD), Electromagnetic Interference (EMI), and Electromagnetic Conductivity (EMC) in miniaturized 3D packaging.Type: ApplicationFiled: October 3, 2011Publication date: April 4, 2013Applicant: International Business Machines CorporationInventors: WILLIAM E. BERNIER, BING DANG, MARIO J. INTERRANTE, JOHN U. KNICKERBOCKER, SON K. TRAN
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Patent number: 8167962Abstract: Pulp production techniques are disclosed. In one embodiment, pulpstone segments are provided, that include proppant grits in the place of some or all of the conventional abrasive typically used in pulpstone applications. The proppant or proppant-abrasive mixture can be combined into a three-dimensional matrix supported by a vitrified bond. Alternative embodiments use proppant grits in an organic bond or a metal bond or a cement bond (each of which may also include abrasive grits in addition to proppant grits). The proportion of proppant grits to abrasive grits can be varied to produce pulp of varying fiber length distribution as required by the end-user (e.g., paper mill). The greater the proppant concentration, the less cutting of the fibers by the conventional abrasive will occur, producing a greater percentage content of longer fibers. Such pulp produces higher quality paper.Type: GrantFiled: April 9, 2008Date of Patent: May 1, 2012Assignees: Saint-Gobain Abrasives, Inc., Saint-Gobain AbrasifsInventors: Glen A. Smith, William E. Bernier
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Patent number: 7566649Abstract: Disclosed is a method of forming an integrated circuit structure that forms lead-free connectors on a device, surrounds the lead-free connectors with a compressible film, connects the device to a carrier (the lead-free connectors electrically connect the device to the carrier), and fills the gaps between the carrier and the device with an insulating underfill.Type: GrantFiled: September 20, 2007Date of Patent: July 28, 2009Assignee: International Business Machines CorporationInventors: William E. Bernier, Tien-Jen Cheng, Marie S. Cole, David E. Eichstadt, Mukta G. Farooq, John A. Fitzsimmons, Lewis S. Goldmann, John U. Knickerbocker, Tasha E. Lopez, David J. Welsh