Abstract: A dielectrically-isolated structure and method of fabricating the same is disclosed wherein the structure includes a layer of silicide which is selectively doped, preferably using an ion implantation process. The doped silicide is then used as the diffusion source for the subsequent formation (through a heat treatment) of various active portions (collector, emitter, drain, source, for example) of a variety of high-voltage, high-speed active devices. The non-doped silicide is advantageously utilized as a low-resistance contact between the buried diffusion region and the surface electrode.

Abstract: A method has been developed for altering the resistivity of selected regions (tubs) in a dielectrically isolated (DI) wafer. Subsequent to the formation of the conventional tub structure, the wafer is patterned and etched to expose selected tubs. These tubs are then etched and selectively implanted and an epitaxial layer of a new resistivity value is grown in the empty tube regions. The resistivity of the epitaxial material may be chosen to alter the conductivity of the selected tub regions.

Abstract: A method of fabricating a dielectrically-isolated structure is disclosed rein the structure includes a layer of silicide which is selectively doped, preferably using an ion implantation process. The doped silicide is then used as the diffusion source for the subsequent formation (through a heat treatment) of various active portions (collector, emitter, drain, source, for example) of a variety of high-voltage, high-speed active devices. The non-doped silicide is advantageously utilized as a low-resistance contact between the buried diffusion region and the surface electrode. In an alternative embodiment, bottom portions of the silicide contiguous to the tub are removed, leaving only vertical silicide portions adjacent to the sidewalls of the dielectrically isolated tub.

Abstract: A method has been developed for providing tub regions with various resistivities in a dielectrically isolated (DI) structure. The starting substrate material is etched to expose the locations designated for a resistivity modification, and epitaxial material of the modified resistivity value is used to fill the exposed tubs. The remainder of the fabrication process follows conventional DI fabrication techniques. The procedure may simply be used to create a DI structure containing both n-type and p-type tube regions. The idea may also be extended, however, to providing separate tubs with, for example, n+ resistivity, n- resistivity, p- resistivity and p+ resistivity, all within the same DI structure.

Abstract: A process for forming a dielectrically isolated wafer is disclosed. In particular, the conventional process is altered to replace the step of growing the thick polysilicon handle layer with the steps of growing a relatively thin conformal coating layer and bonding a single crystal wafer thereto. The wafer will become the substrate of the final device structure. The process of bonding is considered to be more efficient and economical than the prior art polysilicon growth process. Additionally, the tub structures of the wafer bonding process may be exposed to a somewhat lower temperature (for bonding) for shorter period of time than the tub regions of the conventional thick polysilicon DI structures. Therefore, the tub regions will exhibit superior qualities (e.g., less stress, fewer crystal defects) when compared with those formed with the conventional polysilicon growth technique.