Patents by Inventor William J. Cote
William J. Cote has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9213060Abstract: Test structures and method for detecting defects using the same. A probe-able voltage contrast (VC) comb test structure that includes first, second and third probe pads, a comb-like structure including grounded tines, floating tines between the grounded tines, switching devices coupled with an end portion of each floating tine, and connecting the floating tines to the second probe pad, and the third probe pad being a control pad which controls the switching devices. A probe-able VC serpentine test structure that includes first, second, third and fourth probe pads, a comb-like structure including grounded tines, floating tines between the grounded tines and each floating tine connected together between the second and third probe pads, switching devices connected to an end portion of each floating tine and connecting the floating tines to the second and third probe pads, and the fourth probe pad being a control pad which controls the switching devices.Type: GrantFiled: August 24, 2012Date of Patent: December 15, 2015Assignee: International Business Machines CorporationInventors: William J. Cote, Yi Feng, Oliver D. Patterson
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Patent number: 9103875Abstract: Test structures and method for detecting defects using the same. A probe-able voltage contrast (VC) comb test structure that includes first, second and third probe pads, a comb-like structure including grounded tines, floating tines between the grounded tines, switching devices coupled with an end portion of each floating tine, and connecting the floating tines to the second probe pad, and the third probe pad being a control pad which controls the switching devices. A probe-able VC serpentine test structure that includes first, second, third and fourth probe pads, a comb-like structure including grounded tines, floating tines between the grounded tines and each floating tine connected together between the second and third probe pads, switching devices connected to an end portion of each floating tine and connecting the floating tines to the second and third probe pads, and the fourth probe pad being a control pad which controls the switching devices.Type: GrantFiled: August 24, 2012Date of Patent: August 11, 2015Assignee: International Business Machines CorporationInventors: William J. Cote, Yi Feng, Oliver D. Patterson
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Patent number: 9097760Abstract: Test structures and method for detecting defects using the same. A probe-able voltage contrast (VC) comb test structure that includes first, second and third probe pads, a comb-like structure including grounded tines, floating tines between the grounded tines, switching devices coupled with an end portion of each floating tine, and connecting the floating tines to the second probe pad, and the third probe pad being a control pad which controls the switching devices. A probe-able VC serpentine test structure that includes first, second, third and fourth probe pads, a comb-like structure including grounded tines, floating tines between the grounded tines and each floating tine connected together between the second and third probe pads, switching devices connected to an end portion of each floating tine and connecting the floating tines to the second and third probe pads, and the fourth probe pad being a control pad which controls the switching devices.Type: GrantFiled: August 24, 2012Date of Patent: August 4, 2015Assignee: International Business Machines CorporationInventors: William J. Cote, Yi Feng, Oliver D. Patterson
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Publication number: 20150111373Abstract: A method of forming transistors is provided. The method includes forming a plurality of transistor structures to have a plurality of dummy gates on a substrate. Each dummy gate is surrounded by sidewall spacers of a height, which is less than the dummy gate and is different for different transistor structures resulting in divots of different depths above the sidewall spacers. The method then deposits a conformal dielectric layer on top of the dummy gates and inside the divots of the plurality of transistor structures with the conformal dielectric layer having a thickness of at least half of a width of the divots, removes only a portion of the conformal dielectric layer that is on top of the dummy gates to expose the dummy gates; and replaces the dummy gates with a plurality of high-k metal gates.Type: ApplicationFiled: October 18, 2013Publication date: April 23, 2015Applicants: International Business Machines CorporationInventors: William J. Cote, Laertis Economikos, Shom Ponoth, Theodorus E. Standaert, Charan V. Surisetty, Ruilong Xie
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Patent number: 8481423Abstract: Methods of minimizing or eliminating plasma damage to low k and ultra low k organosilicate intermetal dielectric layers are provided. The reduction of the plasma damage is effected by interrupting the etch and strip process flow at a suitable point to add an inventive treatment which protects the intermetal dielectric layer from plasma damage during the plasma strip process. Reduction or elimination of a plasma damaged region in this manner also enables reduction of the line bias between a line pattern in a photoresist and a metal line formed therefrom, and changes in the line width of the line trench due to a wet clean after the reactive ion etch employed for formation of the line trench and a via cavity. The reduced line bias has a beneficial effect on electrical yields of a metal interconnect structure.Type: GrantFiled: September 19, 2007Date of Patent: July 9, 2013Assignees: International Business Machines Corporation, Advanced Micro Devices, Inc.Inventors: John C. Arnold, Griselda Bonilla, William J. Cote, Geraud Dubois, Daniel C. Edelstein, Alfred Grill, Elbert Huang, Robert D. Miller, Satya V. Nitta, Sampath Purushothaman, E. Todd Ryan, Muthumanickam Sankarapandian, Terry A. Spooner, Willi Volksen
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Patent number: 8470706Abstract: Methods of minimizing or eliminating plasma damage to low k and ultra low k organosilicate intermetal dielectric layers are provided. The reduction of the plasma damage is effected by interrupting the etch and strip process flow at a suitable point to add an inventive treatment which protects the intermetal dielectric layer from plasma damage during the plasma strip process. Reduction or elimination of a plasma damaged region in this manner also enables reduction of the line bias between a line pattern in a photoresist and a metal line formed therefrom, and changes in the line width of the line trench due to a wet clean after the reactive ion etch employed for formation of the line trench and a via cavity. The reduced line bias has a beneficial effect on electrical yields of a metal interconnect structure.Type: GrantFiled: September 1, 2012Date of Patent: June 25, 2013Assignees: International Business Machines Corporation, Advanced Micro Devices, Inc.Inventors: John C. Arnold, Griselda Bonilla, William J. Cote, Geraud Dubois, Daniel C. Edelstein, Alfred Grill, Elbert Huang, Robert D. Miller, Satya V. Nitta, Sampath Purushothaman, E. Todd Ryan, Muthumanickam Sankarapandian, Terry A. Spooner, Willi Volksen
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Patent number: 8350583Abstract: Test structures and method for detecting defects using the same. A probe-able voltage contrast (VC) comb test structure that includes first, second and third probe pads, a comb-like structure including grounded tines, floating tines between the grounded tines, switching devices coupled with an end portion of each floating tine, and connecting the floating tines to the second probe pad, and the third probe pad being a control pad which controls the switching devices. A probe-able VC serpentine test structure that includes first, second, third and fourth probe pads, a comb-like structure including grounded tines, floating tines between the grounded tines and each floating tine connected together between the second and third probe pads, switching devices connected to an end portion of each floating tine and connecting the floating tines to the second and third probe pads, and the fourth probe pad being a control pad which controls the switching devices.Type: GrantFiled: August 12, 2009Date of Patent: January 8, 2013Assignee: International Business Machines CorporationInventors: William J. Cote, Yi Feng, Oliver D. Patterson
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Publication number: 20120329269Abstract: Methods of minimizing or eliminating plasma damage to low k and ultra low k organosilicate intermetal dielectric layers are provided. The reduction of the plasma damage is effected by interrupting the etch and strip process flow at a suitable point to add an inventive treatment which protects the intermetal dielectric layer from plasma damage during the plasma strip process. Reduction or elimination of a plasma damaged region in this manner also enables reduction of the line bias between a line pattern in a photoresist and a metal line formed therefrom, and changes in the line width of the line trench due to a wet clean after the reactive ion etch employed for formation of the line trench and a via cavity. The reduced line bias has a beneficial effect on electrical yields of a metal interconnect structure.Type: ApplicationFiled: September 1, 2012Publication date: December 27, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: John C. Arnold, Griselda Bonilla, William J. Cote, Geraud Dubois, Daniel C. Edelstein, Alfred Grill, Elbert Huang, Robert D. Miller, Satya V. Nitta, Sampath Purushothaman, E. Todd Ryan, Muthumanickam Sankarapandian, Terry A. Spooner, Willi Volksen
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Publication number: 20120319715Abstract: Test structures and method for detecting defects using the same. A probe-able voltage contrast (VC) comb test structure that includes first, second and third probe pads, a comb-like structure including grounded tines, floating tines between the grounded tines, switching devices coupled with an end portion of each floating tine, and connecting the floating tines to the second probe pad, and the third probe pad being a control pad which controls the switching devices. A probe-able VC serpentine test structure that includes first, second, third and fourth probe pads, a comb-like structure including grounded tines, floating tines between the grounded tines and each floating tine connected together between the second and third probe pads, switching devices connected to an end portion of each floating tine and connecting the floating tines to the second and third probe pads, and the fourth probe pad being a control pad which controls the switching devices.Type: ApplicationFiled: August 24, 2012Publication date: December 20, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: William J. Cote, Yi Feng, Oliver D. Patterson
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Publication number: 20120319714Abstract: Test structures and method for detecting defects using the same. A probe-able voltage contrast (VC) comb test structure that includes first, second and third probe pads, a comb-like structure including grounded tines, floating tines between the grounded tines, switching devices coupled with an end portion of each floating tine, and connecting the floating tines to the second probe pad, and the third probe pad being a control pad which controls the switching devices. A probe-able VC serpentine test structure that includes first, second, third and fourth probe pads, a comb-like structure including grounded tines, floating tines between the grounded tines and each floating tine connected together between the second and third probe pads, switching devices connected to an end portion of each floating tine and connecting the floating tines to the second and third probe pads, and the fourth probe pad being a control pad which controls the switching devices.Type: ApplicationFiled: August 24, 2012Publication date: December 20, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: William J. Cote, Yi Feng, Oliver D. Patterson
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Publication number: 20120319716Abstract: Test structures and method for detecting defects using the same. A probe-able voltage contrast (VC) comb test structure that includes first, second and third probe pads, a comb-like structure including grounded tines, floating tines between the grounded tines, switching devices coupled with an end portion of each floating tine, and connecting the floating tines to the second probe pad, and the third probe pad being a control pad which controls the switching devices. A probe-able VC serpentine test structure that includes first, second, third and fourth probe pads, a comb-like structure including grounded tines, floating tines between the grounded tines and each floating tine connected together between the second and third probe pads, switching devices connected to an end portion of each floating tine and connecting the floating tines to the second and third probe pads, and the fourth probe pad being a control pad which controls the switching devices.Type: ApplicationFiled: August 24, 2012Publication date: December 20, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: William J. Cote, Yi Feng, Oliver D. Patterson
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Publication number: 20110037493Abstract: Test structures and method for detecting defects using the same. A probe-able voltage contrast (VC) comb test structure that includes first, second and third probe pads, a comb-like structure including grounded tines, floating tines between the grounded tines, switching devices coupled with an end portion of each floating tine, and connecting the floating tines to the second probe pad, and the third probe pad being a control pad which controls the switching devices. A probe-able VC serpentine test structure that includes first, second, third and fourth probe pads, a comb-like structure including grounded tines, floating tines between the grounded tines and each floating tine connected together between the second and third probe pads, switching devices connected to an end portion of each floating tine and connecting the floating tines to the second and third probe pads, and the fourth probe pad being a control pad which controls the switching devices.Type: ApplicationFiled: August 12, 2009Publication date: February 17, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: William J. Cote, Yi Feng, Oliver D. Patterson
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Patent number: 7732866Abstract: Structures and a method are disclosed for grounding gate-stack and/or silicon active region front-end-of-line structures on a silicon-on-insulator (SOI) substrate, which may be used as test structures for VC inspection. In one embodiment, a structure includes a grounded bulk silicon substrate having the SOI substrate thereover, the SOI substrate including a silicon-on-insulator (SOI) layer and a buried oxide (BOX) layer; the silicon active region having at least one finger element within the SOI layer, the at least one finger element isolated by a shallow trench isolation (STI) layer; and a polysilicon ground intersecting the at least one finger element and extending through the STI layer and the BOX layer to the grounded bulk silicon substrate, the polysilicon ground contacting the silicon active region and the grounded bulk silicon substrate.Type: GrantFiled: January 5, 2009Date of Patent: June 8, 2010Assignee: International Business Machines CorporationInventors: William J. Cote, Oliver D. Patterson
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Publication number: 20090146211Abstract: Structures and a method are disclosed for grounding gate-stack and/or silicon active region front-end-of-line structures on a silicon-on-insulator (SOI) substrate, which may be used as test structures for VC inspection. In one embodiment, a structure includes a grounded bulk silicon substrate having the SOI substrate thereover, the SOI substrate including a silicon-on-insulator (SOI) layer and a buried oxide (BOX) layer; the silicon active region having at least one finger element within the SOI layer, the at least one finger element isolated by a shallow trench isolation (STI) layer; and a polysilicon ground intersecting the at least one finger element and extending through the STI layer and the BOX layer to the grounded bulk silicon substrate, the polysilicon ground contacting the silicon active region and the grounded bulk silicon substrate.Type: ApplicationFiled: January 5, 2009Publication date: June 11, 2009Inventors: William J. Cote, Oliver D. Patterson
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Patent number: 7518190Abstract: Structures and a method are disclosed for grounding gate-stack and/or silicon active region front-end-of-line structures on a silicon-on-insulator (SOI) substrate, which may be used as test structures for VC inspection. In one embodiment, a structure includes a grounded bulk silicon substrate having the SOI substrate thereover, the SOI substrate including a silicon-on-insulator (SOI) layer and a buried oxide (BOX) layer; the silicon active region having at least one finger element within the SOI layer, the at least one finger element isolated by a shallow trench isolation (STI) layer; and a polysilicon ground intersecting the at least one finger element and extending through the STI layer and the BOX layer to the grounded bulk silicon substrate, the polysilicon ground contacting the silicon active region and the grounded bulk silicon substrate.Type: GrantFiled: March 22, 2006Date of Patent: April 14, 2009Assignee: International Business Machines CorporationInventors: William J. Cote, Oliver D. Patterson
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Publication number: 20090075472Abstract: Methods of minimizing or eliminating plasma damage to low k and ultra low k organosilicate intermetal dielectric layers are provided. The reduction of the plasma damage is effected by interrupting the etch and strip process flow at a suitable point to add an inventive treatment which protects the intermetal dielectric layer from plasma damage during the plasma strip process. Reduction or elimination of a plasma damaged region in this manner also enables reduction of the line bias between a line pattern in a photoresist and a metal line formed therefrom, and changes in the line width of the line trench due to a wet clean after the reactive ion etch employed for formation of the line trench and a via cavity. The reduced line bias has a beneficial effect on electrical yields of a metal interconnect structure.Type: ApplicationFiled: September 19, 2007Publication date: March 19, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: John C. Arnold, Griselda Bonilla, William J. Cote, Geraud Dubois, Daniel C. Edelstein, Alfred Grill, Elbert Huang, Robert D. Miller, Satya V. Nitta, Sampath Purushothaman, E. Todd Ryan, Muthumanickam Sankarapandian, Terry A. Spooner, Willi Volksen
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Patent number: 7480990Abstract: Methods for forming conductor contacts provide for etching through a capping layer located upon a conductor contact region within a substrate. A first pair of methods provide for etching through at least a lower thickness of the capping layer with other than a reactive ion etch to provide an exposed conductor contact region. A partially overlapping second pair of methods provides for converting at least an upper thickness of the capping layer to a converted material layer that is removed incident to providing an exposed conductor contact region. As adjunct to any of the methods, a liner layer is formed and located upon the exposed conductor contact region in absence of an undesirable reactive environment.Type: GrantFiled: January 6, 2006Date of Patent: January 27, 2009Assignee: International Business Machines CorporationInventors: John A. Fitzsimmons, William J. Cote, Nancy A. Greco, Thomas H. Ivers, Steven Moskowitz
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Patent number: 7323382Abstract: A decoupling capacitor is provided for a semiconductor device and may include a first low dielectric insulator layer and a low resistance conductor formed into at least two interdigitized patterns on the surface of the first low dielectric insulator in a single interconnect plane. A high dielectric constant material may be provided between the two patterns. A circuit for testing a plurality of these capacitors is also provided which includes a charge monitoring circuit, a coupling circuit and a control circuit.Type: GrantFiled: February 16, 2007Date of Patent: January 29, 2008Assignee: International Business Machines CorporationInventors: Kerry Bernstein, John A. Bracchitta, William J. Cote, Tak H. Ning, Wilbur D. Pricer
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Patent number: 7195971Abstract: A decoupling capacitor is provided for a semiconductor device and may include a first low dielectric insulator layer and a low resistance conductor formed into at least two interdigitized patterns on the surface of the first low dielectric insulator in a single interconnect plane. A high dielectric constant material may be provided between the two patterns. A circuit for testing a plurality of these capacitors is also provided which includes a charge monitoring circuit, a coupling circuit and a control circuit.Type: GrantFiled: February 28, 2005Date of Patent: March 27, 2007Assignee: International Business Machines CorporationInventors: Kerry Bernstein, John A. Bracchitta, William J. Cote, Tak H. Ning, Wilbur D. Pricer
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Patent number: 7030031Abstract: This invention relates to the manufacture of dual damascene interconnect structures in integrated circuit devices. Specifically, a method is disclosed for forming a single or dual damascene structure in a low-k dielectric thin film utilizing a planarizing material and a diffusion barrier material. In a preferred dual damascene embodiment of this method, the vias are formed first in the dielectric material, then the planarizing material is deposited in the vias and on the dielectric material, and the barrier material is deposited on the planarizing material. The trenches are then formed lithographically in the imaging material, etched through the barrier material into the planarizing material, and the trench pattern is transferred to the dielectric material. During and following the course of these etch steps, the imaging, barrier and planarizing materials are removed. The resultant dual damascene structure may then be metallized.Type: GrantFiled: June 24, 2003Date of Patent: April 18, 2006Assignee: International Business Machines CorporationInventors: William C. Wille, Daniel C. Edelstein, William J. Cote, Peter E. Biolsi, John Fritche, Allan W. Upham