Abstract: A decoupling capacitor is provided for a semiconductor device and may include a first low dielectric insulator layer and a low resistance conductor formed into at least two interdigitized patterns on the surface of the first low dielectric insulator in a single interconnect plane. A high dielectric constant material may be provided between the two patterns. A circuit for testing a plurality of these capacitors is also provided which includes a charge monitoring circuit, a coupling circuit and a control circuit.

Abstract: This invention relates to the manufacture of dual damascene interconnect structures in integrated circuit devices. Specifically, a method is disclosed for forming a single or dual damascene structure in a low-k dielectric thin film utilizing a planarizing material and a diffusion barrier material. In a preferred dual damascene embodiment of this method, the vias are formed first in the dielectric material, then the planarizing material is deposited in the vias and on the dielectric material, and the barrier material is deposited on the planarizing material. The trenches are then formed lithographically in the imaging material, etched through the barrier material into the planarizing material, and the trench pattern is transferred to the dielectric material. During and following the course of these etch steps, the imaging, barrier and planarizing materials are removed. The resultant dual damascene structure may then be metallized.

Abstract: A tantalum-based liner for copper metallurgy is selectively removed by chemical-mechanical planarization (CMP) in an acidic slurry of an oxidizer such as hydrogen peroxide, deionized water, a corrosion inhibitor such as BTA, and a surfactant such as Duponol SP, resulting in a high removal rate of the liner without appreciable removal of the exposed copper and with minimal dishing.

Abstract: A decoupling capacitor is provided for a semiconductor device and may include a first low dielectric insulator layer and a low resistance conductor formed into at least two interdigitized patterns on the surface of the first low dielectric insulator in a single interconnect plane. A high dielectric constant material may be provided between the two patterns. A circuit for testing a plurality of these capacitors is also provided which includes a charge monitoring circuit, a coupling circuit and a control circuit.

Abstract: A decoupling capacitor is provided for a semiconductor device and may include a first low dielectric insulator layer and a low resistance conductor formed into at least two interdigitized patterns on the surface of the first low dielectric insulator in a single interconnect plane. A high dielectric constant material may be provided between the two patterns. A circuit for testing a plurality of these capacitors is also provided which includes a charge monitoring circuit, a coupling circuit and a control circuit.

Abstract: A process for forming a damascene structure includes depositing a bilayer comprising a first dielectric layer and a second dielectric layer onto a substrate, wherein the first layer has a dielectric constant higher than the second layer, and wherein the second layer is selected from a low k dielectric material comprising Si, C, O and H. The multi-step damascene structure is patterned into the dielectric bilayer using highly selective anisotropic reactive ion etching. Photoresist, polymers and post etch residues are removed from the substrate using a plasma ashing process without damaging the underlying dielectric layers.

Abstract: A process for forming a damascene structure includes depositing a bilayer comprising a first dielectric layer and a second dielectric layer onto a substrate, wherein the first layer has a dielectric constant higher than the second layer, and wherein the second layer is selected from a low k dielectric material comprising Si, C, O and H. The multi-step damascene structure is patterned into the dielectric bilayer using highly selective anisotropic reactive ion etching. Photoresist, polymers and post etch residues are removed from the substrate using a plasma ashing process without damaging the underlying dielectric layers.

Abstract: A process of depositing a low k dielectric film on a substrate includes using plasma enhance chemical vapor deposition to deposit a hydrogenated oxidized silicon carbon film. The process includes flowing a precursor gas containing Si, C, H and an oxygen-providing gas into the PECVD chamber. The precursor gas and the oxygen-providing gas are substantially free from nitrogen. The oxygen-providing gas is selected from the group consisting of oxygen, carbon monoxide, carbon dioxide, ozone, water vapor and a combination of at least one of the foregoing.

Abstract: A decoupling capacitor is provided for a semiconductor device and may include a first low dielectric insulator layer and a low resistance conductor formed into at least two interdigitized patterns on the surface of the first low dielectric insulator in a single interconnect plane. A high dielectric constant material may be provided between the two patterns. A circuit for testing a plurality of these capacitors is also provided which includes a charge monitoring circuit, a coupling circuit and a control circuit.

Abstract: A tantalum-based liner for copper metallurgy is selectively removed by chemical-mechanical planarization (CMP) in an acidic slurry of an oxidizer such as hydrogen peroxide, deionized water, a corrosion inhibitor such as BTA, and a surfactant such as Duponol SP, resulting in a high removal rate of the liner without appreciable removal of the exposed copper and with minimal dishing.

Abstract: A tantalum-based liner for copper metallurgy is selectively removed by chemical-mechanical planarization (CMP) in an acidic slurry of an oxidizer such as hydrogen peroxide, deionized water, a corrosion inhibitor such as BTA, and a surfactant such as DUPONOL SP, resulting in a high removal rate of the liner without appreciable removal of the exposed copper and with minimal dishing.

Abstract: Slurry compositions comprising an oxidizing agent, copper corrosion inhibitor, abrasive particles; surface active agent and polyelectrolyte are useful for polishing or planarizing chip interconnect/wiring material such as Al, W and especially Cu.

Abstract: The present invention is embodied in a process for creating a dual damascene structure. The process includes the steps of forming a photoresist film on a substrate, pattern exposing the photoresist film to form a first pattern in the photoresist film, and forming an etch resistant layer in the first pattern. The resistant layer is resistant to a further pattern exposure and etching. The photoresist film is pattern exposed a second time to form a second pattern in the photoresist film. The sections of the photoresist film corresponding to the second pattern are removed and the substrate is etched to form the second pattern in the substrate. The resistant layer is removed and the substrate is etched to form the first pattern in the substrate. Finally, the remaining photoresist film is removed from the substrate.

Abstract: The present invention is embodied in a process for creating a dual damascene structure. The process includes the steps of forming a photoresist film on a substrate, pattern exposing the photoresist film to form a first pattern in the photoresist film, and forming an etch resistant layer in the first pattern. The resistant layer is resistant to a further pattern exposure and etching. The photoresist film is pattern exposed a second time to form a second pattern in the photoresist film. The sections of the photoresist film corresponding to the second pattern are removed and the substrate is etched to form the second pattern in the substrate. The resistant layer is removed and the substrate is etched to form the first pattern in the substrate. Finally, the remaining photoresist film is removed from the substrate.

Abstract: The invention is directed to a semi-conductor wafer processing machine including an arm having a wafer carrier disposed at one end. The wafer carrier is rotatable with the rotating motion imparted to a semi-conductor wafer held thereon. In first embodiment, the machine further includes a rotatable polishing pad having an upper surface divided into a plurality of wedge-shaped sections, including an abrasion section and a polishing section. The abrasion section has a relatively rough texture and the polishing section has a relatively fine texture as compared to each other. In an alternative embodiment, the pad includes an underlayer and surface layer. The surface layer includes two sections of differing hardness, both of which are harder than the underlayer. Alternatively, the surface layer may include one relatively hard section, and the underlayer may include two sections, one of which has the same hardness as the surface layer and the other of which is softer than the surface layer.

Abstract: A method and apparatus for improved control of polishing in chemical-mechanical polishing operations is provided. The polishing is controlled by applying different amounts of pressure to the surface of a substrate during polishing. A polishing pad which includes raised portions is used to apply the varying amounts of pressure. In addition, the position, size and height of the raised portions is used to affect the amount of pressure applied.

Abstract: The invention is directed to a semi-conductor wafer processing machine including an arm having a wafer carrier disposed at one end. The wafer carrier is rotatable with the rotating motion imparted to a semi-conductor wafer held thereon. In first embodiment, the machine further includes a rotatable polishing pad having an upper surface divided into a plurality of wedge-shaped sections, including an abrasion section and a polishing section. The abrasion section has a relatively rough texture and the polishing section has a relatively fine texture as compared to each other. In an alternative embodiment, the pad includes an underlayer and surface layer. The surface layer includes two sections of differing hardness, both of which are harder than the underlayer. Alternatively, the surface layer may include one relatively hard section, and the underlayer may include two sections, one of which has the same hardness as the surface layer and the other of which is softer than the surface layer.

Abstract: An apparatus and method for determining a selected endpoint in the polishing of layers on a workpiece in a chemical/mechanical polishing apparatus where the workpiece is rotated by a motor against a polishing pad. When a difficult to polish layer, i.e., one requiring a chemical change in a surface skin of the layer which skin is then abraded away by a mechanical process is removed from a more easy to polish surface, i.e., one that relies solely on mechanical abrasion and does not need to have a chemically converted skin thereon. The power required to maintain a set rotational speed in a motor rotating the workpiece significantly drops when the difficult to polish layer is removed. This current drop is used to detect the point at which the polishing must be stopped to avoid over polishing effects, i.e., dishing or thinning or removal of the more easily removed underlying material. Thus, an end point in the process can be established.

Abstract: Electrically conducting vias and lines are created by a three step process. First, a controlled amount of a soft, low resistivity metal (12) is deposited in a trench or hole to a point below the top surface of the dielectric (10) in which the trench or hole is formed. Subsequently, the low resistivity metal (12) is overcoated with a hard metal (16) such as CVD tungsten. Finally, chemical-mechanical polishing is used to planarize the structure. The hard metal (16) serves the function of protecting the low resistivity metal (12) from scratches and corrosion which would ordinarily be encountered if the low resistivity metal were subjected to the harsh chemical-mechanical polishing slurries. An ideal method for partially filling trenches or holes in a substrate is by sputtering at elevated temperatures such that metallization at the bottom of a trench or hole separates from metallization on a top surface adjacent the trench or hole.

Abstract: In a chem-mech polishing process for planarizing insulators such as silicon oxide and silicon nitride, a pool of slurry is utilized at a temperature between 85° F.-95° F. The slurry particulates (e.g. silica) have a hardness commensurate to the hardness of the insulator to be polished. Under these conditions, wafers can be polished at a high degree of uniformity more economically (by increasing pad lifetime), without introducing areas of locally incomplete polishing.