Abstract: A moat is preferably created in a region of an insulation layer on a wafer that will be destroyed when the wafer is cut. The integrated circuit includes a first metal pattern in an active region and a second metal pattern on the moat island. An insulating layer is conformally deposited and chemical-mechanical polishing is performed thereon. The polish rate above the second metal pattern is significantly higher than above the first metal pattern. Polishing is monitored and ended when the second metal pattern is exposed, achieving planarization of the top surface in the active region of the integrated circuit. Monitoring may be visual or electrical. For visual monitoring, the second metal pattern preferably comprises a visually noticeable metal in relation to the insulating layer.

Abstract: A method of forming a plurality of conductive studs within a non-planar insulator layer (e.g., PSG or BPSG) disposed between a first series of conductive structures arranged on a substrate and metal lines formed on the upper surface of the insulator layer. Vertical vias are defined through the insulator layer to expose at least one of the first conductive structures on the substrate. A conformal metal layer (e.g., CVD W) is deposited on the insulator layer to fill the vias. Then, the metal layer and the insulator layer subjected to a polish etch in the presence of an abrasive slurry, to remove portions of the metal layer outside of the vias while simultaneously planarizing the insulator layer.

Abstract: A method for dry etching metals that form low volatility chlordes, in which Z-Cl reaction products are controllably introduced into a conventional Cl-based plasma independent of the workpiece. The Z-Cl products (e.g., AlCl.sub.3, GaCl.sub.3, etc.) are metal chlorides that have both electron acceptor and chloride donor properties. Thus, metals M (e.g., cobalt, copper and nickel) that usually produce low volatility chlorides can be controllably complexed to form high volatility Z.sub.x Cl.sub.y M.sub.z reaction products.

Abstract: In a chem-mech polishing process for planarizing insulators such as silicon oxide and silicon nitride, a pool of slurry is utilized at a temperature between 85.degree. F.-95.degree. F. The slurry particulates (e.g. silica) have a hardness commensurate to the hardness of the insulator to be polished. Under these conditions, wafers can be polished at a high degree of uniformity more economically (by increasing pad lifetime), without introducing areas of locally incomplete polishing.

Abstract: A conformal organic layer is used to define spacers on the sidewalls of an organic mandrel. The organic layer (e.g., parylene) can be deposited at low temperatures, and as such is compatible with temperature-sensitive mandrel materials that reflow at high deposition temperatures. The conformal organic material can be dry etched as the same rate as the organic mandrels, while being resistant to wet strip solvents that remove the organic mandrels. This series of etch characteristics make the organic mandrel-organic spacer combination compatible with a host of masking applications.

Abstract: A method for anisotropically etching a thick tungsten layer atop a thin underlayer comprised of titanium nitride, by exposure to a gaseous plasma comprised of a binary mixture of chlorine gas and oxygen, wherein oxygen comprises approximately 25%-45% of the mixture by volume. This plasma provides a combination of high tungsten etch rate, highly uniform etching, anisotropic profiles, and high etch rate ratio to underlaying glass passivation layers.