Patents by Inventor William Paul Hovis

William Paul Hovis has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200373224
    Abstract: Integrated circuit decoupling capacitance systems, arrangements, and assemblies are discussed herein. In one example, an assembly includes an integrated circuit device comprising a plurality of through silicon vias (TSVs) coupled to corresponding voltage domains of the integrated circuit device. The assembly includes one or more capacitive elements external to the integrated circuit device and conductively coupled to selected ones of the TSVs.
    Type: Application
    Filed: May 21, 2019
    Publication date: November 26, 2020
    Inventors: Gregory M. Daly, William Paul Hovis
  • Publication number: 20200373260
    Abstract: Integrated circuit device carriers and packaging assemblies which have attached decoupling capacitance are discussed herein. In one example, an assembly includes a package assembly comprising a carrier circuit board and an integrated circuit device coupled to a first side of the carrier circuit board. The assembly includes decoupling capacitors for the integrated circuit device are coupled to a second side of the carrier circuit board opposite from at least a portion of a footprint of the integrated circuit device on the carrier circuit board. A motherboard can be coupled to the package assembly and have at least one motherboard substrate layer facing the decoupling capacitors.
    Type: Application
    Filed: May 24, 2019
    Publication date: November 26, 2020
    Inventors: William Paul Hovis, Gregory M. Daly, Rich Tat An
  • Publication number: 20200373285
    Abstract: Integrated circuit device carriers and packaging assemblies which have attached decoupling capacitance are discussed herein. In one example, an assembly includes a package assembly coupled to a motherboard and comprising a carrier circuit board and an integrated circuit device coupled to a first side of the carrier circuit board. The assembly also includes decoupling capacitors for the integrated circuit device conductively coupled between the motherboard and a second side of the carrier circuit board opposite from at least a portion of a footprint of the integrated circuit device on the carrier circuit board.
    Type: Application
    Filed: May 24, 2019
    Publication date: November 26, 2020
    Inventors: William Paul Hovis, Gregory M. Daly, Rich Tat An
  • Patent number: 10755020
    Abstract: Computing assemblies, such as blade servers, can comprise a plurality of modular computing elements coupled onto an associated circuit board assembly. Assemblies and systems having enhanced individual computing module placement and arrangement are discussed herein, as well as example systems and operations to manufacture such assemblies. In one example, a method includes executing a performance test on a plurality of computing modules to determine at least variability in power consumption across the plurality of computing modules, and binning the plurality of computing modules according to graduated levels of the variability in power consumption. The method also includes selecting from among the graduated levels for placement in an assembly of ones of the computing modules in a progressively lower power consumption arrangement with relation to an airflow of the assembly.
    Type: Grant
    Filed: April 3, 2019
    Date of Patent: August 25, 2020
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Andres Felipe Hernandez Mojica, William Paul Hovis, Garrett Douglas Blankenburg
  • Publication number: 20190278741
    Abstract: An example method for adjusting operation of an integrated circuit includes testing a plurality of electronic elements of the integrated circuit including one or more redundant electronic elements designated as inactive according to a manufacturer's default configuration of the integrated circuit to determine one or more operating parameters of the integrated circuit. The method further includes selecting a subset of electronic elements from the plurality of electronic elements based on the one or more operating parameters, wherein the subset of electronic elements is designated as active according to an updated configuration of the integrated circuit, and controlling operation of the integrated circuit using the updated configuration instead of the manufacturer's default configuration.
    Type: Application
    Filed: May 2, 2018
    Publication date: September 12, 2019
    Applicant: Microsoft Technology Licensing, LLC
    Inventors: William Paul HOVIS, Peter A. ATKINSON, Robert James RAY, Garrett Douglas BLANKENBURG, Andres Felipe HERNANDEZ
  • Patent number: 10338670
    Abstract: Voltage adjustment techniques for computing systems and processing devices are presented herein. In one example, a method of determining operating voltages for a processing device includes executing a voltage adjustment process to determine at least one input voltage for the processing device lower than a manufacturer specified operating voltage. During the voltage adjustment process, the method includes applying incrementally adjusted input voltages to the processing device, operating the processing device according to a functional test that exercises the processing device in context with associated system elements of a computing assembly, and monitoring for operational failures of at least the processing device during application of each of the incrementally adjusted input voltages.
    Type: Grant
    Filed: June 10, 2016
    Date of Patent: July 2, 2019
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: William Paul Hovis, Garrett Douglas Blankenburg, Peter Anthony Atkinson, Robert James Ray, Andres Felipe Hernandez Mojica, Samy Boshra-Riad, Erng-Sing Wee, Brian Keith Langendorf
  • Publication number: 20190171278
    Abstract: Power reduction and voltage adjustment techniques for computing systems and processing devices are presented herein. In one example, a method includes executing a voltage characterization service for a processing device of a computing apparatus to determine at least one supply voltage for the processing device, the voltage characterization service comprising a functional test that exercises the processing device at iteratively adjusted voltages in context with associated system elements of the computing apparatus. During execution of the voltage characterization service, the method includes monitoring for operational failures of at least the processing device, and responsive to the operational failures, determining at least one resultant supply voltage.
    Type: Application
    Filed: January 28, 2019
    Publication date: June 6, 2019
    Inventors: William Paul Hovis, Garrett Douglas Blankenburg, Peter Anthony Atkinson, Robert James Ray, Andres Felipe Hernandez Mojica, Samy Boshra-Riad, Erng-Sing Wee, Brian Keith Langendorf
  • Patent number: 10310572
    Abstract: Thermal reduction and voltage adjustment techniques for computing systems and processing devices are presented herein. In a first example, a method of operating a voltage control system for a processing device includes operating the processing device in a computing assembly at a selected performance level, the processing device supplied with at least one input voltage at a first voltage level. The method includes monitoring thermal information associated with the computing assembly, and when the thermal information indicates a temperature associated with the computing assembly exceeds a threshold temperature, adjusting the at least one input voltage level supplied to the processing device to a second voltage level lower than the first voltage level and continuing to operate the processing device at the selected performance level.
    Type: Grant
    Filed: June 10, 2016
    Date of Patent: June 4, 2019
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: William Paul Hovis, Garrett Douglas Blankenburg, Peter Anthony Atkinson, Robert James Ray, Andres Felipe Hernandez Mojica, Samy Boshra-Riad, Erng-Sing Wee, Brian Keith Langendorf
  • Patent number: 10268248
    Abstract: A method for controlling a cooling system for a device includes determining a power load of the processing system, determining a power load of the device, setting a first thermal setpoint based at least in part on the power load, determining a temperature of the device, adjusting a response of the cooling system based at least in part on the first thermal setpoint, detecting a change in the power load of the device to a higher power load having a higher magnitude acoustic response, in response to detecting the change in the power load, setting a second thermal setpoint having a lower magnitude acoustic response at the higher power load, the second thermal setpoint being based at least in part on a determined second corresponding acoustic response curve, and adjusting the response of the cooling system based at least in part on the second thermal setpoint.
    Type: Grant
    Filed: February 6, 2017
    Date of Patent: April 23, 2019
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: William Paul Hovis, Andres Hernandez, Peter Atkinson, Gregory M. Daly, Garrett Blankenburg
  • Patent number: 10248186
    Abstract: Power reduction and voltage adjustment techniques for computing systems and processing devices are presented herein. In one example, a method includes receiving a voltage characterization service over a communication interface of the computing apparatus as transferred by a deployment platform remote from the computing apparatus. The method includes executing the voltage characterization service for a processing device of the computing apparatus to determine at least one input voltage for the processing device lower than a manufacturer specified operating voltage, the voltage characterization service comprising a functional test that exercises the processing device at iteratively adjusted voltages in context with associated system elements of the computing apparatus.
    Type: Grant
    Filed: June 10, 2016
    Date of Patent: April 2, 2019
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: William Paul Hovis, Garrett Douglas Blankenburg, Peter Anthony Atkinson, Robert James Ray, Andres Felipe Hernandez Mojica, Samy Boshra-Riad, Erng-Sing Wee, Brian Keith Langendorf
  • Patent number: 10209726
    Abstract: Secure voltage adjustment techniques for computing systems and processing devices are presented herein. In one example, a method of controlling operating voltages for a processing device includes initializing a security portion of the processing device after application of input voltages to the processing device as supplied by voltage regulation circuitry according to voltage identifiers (VIDs) established for the processing device. The method includes, in the security portion, generating adjusted input voltages based on at least the VIDs and authenticated voltage offset information stored according to a digitally signed security process, and instructing the voltage regulation circuitry to supply the adjusted input voltages to the processing device.
    Type: Grant
    Filed: June 10, 2016
    Date of Patent: February 19, 2019
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: William Paul Hovis, Garrett Douglas Blankenburg, Peter Anthony Atkinson, Robert James Ray, Andres Felipe Hernandez Mojica, Samy Boshra-Riad, Erng-Sing Wee, Brian Keith Langendorf
  • Publication number: 20190050039
    Abstract: A computing device is provided that includes a processor, a primary power supply, and a voltage regulation module. The voltage regulation module is configured to determine a load line for the processor and monitor a voltage and a current to the processor. While monitoring the voltage and current, the voltage regulation module is further configured to regulate the voltage to the processor to trend toward a voltage setpoint defined by the load line. While regulating the voltage, the voltage regulation module is further configured to clamp the load line at a clamping voltage to limit the regulated voltage output by the voltage regulation module from falling below a predetermined device minimum operation voltage when the monitored current exceeds a device maximum current value. The voltage regulation module is further configured to output electrical power at the regulated voltage to the processor.
    Type: Application
    Filed: December 13, 2017
    Publication date: February 14, 2019
    Applicant: Microsoft Technology Licensing, LLC
    Inventors: Peter ATKINSON, Steven William RANTA, Francine Mary SHAMMAMI, William Paul HOVIS
  • Publication number: 20180032114
    Abstract: A method for controlling a cooling system for a device includes determining a power load of the processing system, determining a power load of the device, setting a first thermal setpoint based at least in part on the power load, determining a temperature of the device, adjusting a response of the cooling system based at least in part on the first thermal setpoint, detecting a change in the power load of the device to a higher power load having a higher magnitude acoustic response, in response to detecting the change in the power load, setting a second thermal setpoint having a lower magnitude acoustic response at the higher power load, the second thermal setpoint being based at least in part on a determined second corresponding acoustic response curve, and adjusting the response of the cooling system based at least in part on the second thermal setpoint.
    Type: Application
    Filed: February 6, 2017
    Publication date: February 1, 2018
    Applicant: Microsoft Technology Licensing, LLC
    Inventors: William Paul Hovis, Andres Hernandez, Peter Atkinson, Gregory M. Daly, Garrett Blankenburg
  • Publication number: 20170357298
    Abstract: Thermal reduction and voltage adjustment techniques for computing systems and processing devices are presented herein. In a first example, a method of operating a voltage control system for a processing device includes operating the processing device in a computing assembly at a selected performance level, the processing device supplied with at least one input voltage at a first voltage level. The method includes monitoring thermal information associated with the computing assembly, and when the thermal information indicates a temperature associated with the computing assembly exceeds a threshold temperature, adjusting the at least one input voltage level supplied to the processing device to a second voltage level lower than the first voltage level and continuing to operate the processing device at the selected performance level.
    Type: Application
    Filed: June 10, 2016
    Publication date: December 14, 2017
    Inventors: William Paul Hovis, Garrett Douglas Blankenburg, Peter Anthony Atkinson, Robert James Ray, Andres Felipe Hernandez Mojica, Samy Boshra-Riad, Erng-Sing Wee, Brian Keith Langendorf
  • Publication number: 20170357311
    Abstract: Power reduction and voltage adjustment techniques for computing systems and processing devices are presented herein. In one example, a method includes receiving a voltage characterization service over a communication interface of the computing apparatus as transferred by a deployment platform remote from the computing apparatus. The method includes executing the voltage characterization service for a processing device of the computing apparatus to determine at least one input voltage for the processing device lower than a manufacturer specified operating voltage, the voltage characterization service comprising a functional test that exercises the processing device at iteratively adjusted voltages in context with associated system elements of the computing apparatus.
    Type: Application
    Filed: June 10, 2016
    Publication date: December 14, 2017
    Inventors: William Paul Hovis, Garrett Douglas Blankenburg, Peter Anthony Atkinson, Robert James Ray, Andres Felipe Hernandez Mojica, Samy Boshra-Riad, Erng-Sing Wee, Brian Keith Langendorf
  • Publication number: 20170357310
    Abstract: Voltage adjustment techniques for computing systems and processing devices are presented herein. In one example, a method of determining operating voltages for a processing device includes executing a voltage adjustment process to determine at least one input voltage for the processing device lower than a manufacturer specified operating voltage. During the voltage adjustment process, the method includes applying incrementally adjusted input voltages to the processing device, operating the processing device according to a functional test that exercises the processing device in context with associated system elements of a computing assembly, and monitoring for operational failures of at least the processing device during application of each of the incrementally adjusted input voltages.
    Type: Application
    Filed: June 10, 2016
    Publication date: December 14, 2017
    Inventors: William Paul Hovis, Garrett Douglas Blankenburg, Peter Anthony Atkinson, Robert James Ray, Andres Felipe Hernandez Mojica, Samy Boshra-Riad, Erng-Sing Wee, Brian Keith Langendorf
  • Publication number: 20170357279
    Abstract: Secure voltage adjustment techniques for computing systems and processing devices are presented herein. In one example, a method of controlling operating voltages for a processing device includes initializing a security portion of the processing device after application of input voltages to the processing device as supplied by voltage regulation circuitry according to voltage identifiers (VIDs) established for the processing device. The method includes, in the security portion, generating adjusted input voltages based on at least the VIDs and authenticated voltage offset information stored according to a digitally signed security process, and instructing the voltage regulation circuitry to supply the adjusted input voltages to the processing device.
    Type: Application
    Filed: June 10, 2016
    Publication date: December 14, 2017
    Inventors: William Paul Hovis, Garrett Douglas Blankenburg, Peter Anthony Atkinson, Robert James Ray, Andres Felipe Hernandez Mojica, Samy Boshra-Riad, Erng-Sing Wee, Brian Keith Langendorf
  • Patent number: 8108647
    Abstract: A communications architecture utilizes modules arranged in a daisy-chain, each module supporting multiple input and output ports. Point-to-point links are arranged so that a first output link of each of multiple modules connects to the next module in the chain, and a second output link connects to a module after it, and inputs arranged similarly, so that any single module can be by-passed in the event of malfunction. Multiple chains may be cross-linked and/or serviced by hubs or chains of hubs. Preferably, the redundant links are used in a non-degraded operating mode to provide higher bandwidth and/or reduced latency of communication. The exemplary embodiment is a memory subsystem in which the modules are buffered memory chips.
    Type: Grant
    Filed: January 29, 2009
    Date of Patent: January 31, 2012
    Assignee: International Business Machines Corporation
    Inventors: Gerald Keith Bartley, Darryl John Becker, John Michael Borkenhagen, Philip Raymond Germann, William Paul Hovis, Mark Owen Maxson
  • Patent number: 7935629
    Abstract: An apparatus and method are disclosed for an improved semiconductor interconnect scheme using a simplified process. In an embodiment of the apparatus, a polysilicon shape is formed on a silicon area. The polysilicon shape is created having a bridging vertex. When a spacer is created on the polysilicon shape, the spacer width is formed to be small enough near the bridging vertex to allow a silicide bridge to form that creates an electrical coupling between the silicon area and the bridging vertex. Semiconductor devices and circuits are created using the improved semiconductor interconnect scheme using the simplified process.
    Type: Grant
    Filed: October 22, 2007
    Date of Patent: May 3, 2011
    Assignee: International Business Machines Corporation
    Inventors: Todd Alan Christensen, Richard Lee Donze, William Paul Hovis, Terrance Wayne Kueper, John Edward Sheets, II
  • Patent number: 7908443
    Abstract: A memory controller optimizes execution of a read/modify/write command by breaking the RMW command into separate and unique read and write commands that do not need to be executed together, but just need to be executed in the proper sequence. The most preferred embodiments use a separate RMW queue in the controller in conjunction with the read queue and write queue. In other embodiments, the controller places the read and write portions of the RMW into the read and write queue, but where the write queue has a dependency indicator associated with the RMW write command in the write queue to insure the controller maintains the proper execution sequence. The embodiments allow the memory controller to translate RMW commands into read and write commands with the proper sequence of execution to preserve data coherency.
    Type: Grant
    Filed: June 10, 2008
    Date of Patent: March 15, 2011
    Assignee: International Business Machines Corporation
    Inventors: Philip Rogers Hillier, III, William Paul Hovis, Joseph Allen Kirscht